Ahold - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.5.
AHOLD
AHOlD Address Hold
Causes the CPU to float its address bus.
Output from 82496 Cache Controller (pin BI8), Input to Pentium processor (pin
lO2)
Synchronous to ClK
Signal Description
AHOLD is the CPU bus address hold request. The 82496 Cache Controller will drive AHOLD
active when it needs to perform CPU inquire, back-invalidation, flush, or sync cycles. When
AHOLD is active, the CPU does not drive the CPU address bus. During address hold the
82496 Cache Controller will drive the address bus and address parity bits.
When Driven
The 82496 Cache Controller activates AHOLD during snoop write back cycles, replacement
write back cycles, reset, initialization, and self test.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CAHOlD Reflects the value of AHOlD on the memory bus (except during BIST).
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