Intel 82496 CACHE CONTROLLER User Manual page 284

HARDWARE INTERFACE
5.2.2.99.
MRO#
MRO# Memory Read-Only
Designates current line as read-only.
Input to 82496 Cache Controller (pin K02)
Synchronous to ClK
.Internal Pull-up
Signal Description
MRO# is sampled at the closing of the cache ability window (on KWEND# activation). If
sampled active, MRO# causes the current line fill to the 82496 Cache Controller/82491 Cache
SRAM cache to be put in the Shared state with the read only bit set. Read only code is, in tum,
cached in the Pentium processor code cache. Read only data is NOT cached in the Pentium
processor data cache. Writes during which MRO# is sampled active during KWEND# should
not initiate a read for ownership.
Once MRO# is sampled active on KWEND# activation, KEN# to the CPU is driven inactive
regardless of the state of MKEN# for data accesses (CD/C#=l). For code accesses (CD/C#=O)
in which MRO# is sampled active on KWEND# activation, the value of KEN# driven to the
CPU depends upon the value of MKEN#. MKEN# does, however, determine whether the
82496 Cache Controller caches the read-only line. If MKEN# is returned active, the 82496
Cache Controller/82491 Cache SRAM requires an entire cache line from the memory bus.
"Read-Only" cache lines are placed in the [S] state.
If MRO# is returned active during KWEND#, DRCTM# and MWB/WT# are ignored during
SWEND#.
The linefill portion of an allocation may be placed in the read only state by returning MRO#
active during KWEND# of the write. MRO# is ignored at KWEND# of the allocation (linefill).
MRO# must be returned to the 82496 Cache Controller at least one CLK before BRDY# is
returned to the CPU so KEN# can be sampled properly (when CD/C#=l and CCACHE#=O).
There is one read-only bit per 82496 Cache Controller tag. If the cache is configured to have
two lines per sector, there is one read-only bit per sector (e.g. two lines). Therefore, in a two
lines per sector configuration, the two lines must be both read only or neither read only.
WARNING
If the first line in a sector is cached as read only (the read only bit is set), the
82496 Cache Controller will allow the second to be cached in [E] or [M]
states. It is the MBCs responsibility to insure that this does not occur by
asserting MRO# for BOTH lines in a read only sector!
When Sampled
MRO# and MKEN# are sampled on the first CLK in which KWEND# is sampled active. For
cacheable read miss cycles, they are sampled with the KWEND# of the read. For write-through
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