Intel 82496 CACHE CONTROLLER User Manual page 297

HARDWARE INTERFACE
5.2.2.108. NENE#
NENE# Next Near
Indicates cycle address is "near" previous address.
Output from 82496 Cache Controller (pin E06)
Synchronous to ClK
NENE# Signal Description
NENE# is asserted by the 82496 Cache Controller to indicate that the memory address of a
given memory cycle is in the same 2K DRAM page as the address of the previous cycle. This
information may be used by the MBC to optimize accesses to page-mode or static-column
DRAMs.
NENE# must be ignored, by the MBC if the memory bus accesses to the same page are not
consecutive. For example, if a snoop write back cycle is issued between two normal memory
bus cycles, the NENE# signal may go active, but has no meaning since the snoop address
interfered with the "near" address checking.
When Driven
NENE# is valid with CADS# and SNPADS# and remains valid until CNA# or CRDY# is
asserted.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS# Address and cycle specification signals (i.e., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KlOCK#, MAP, MBT[3:0j, MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
CNA#
NENE# may change its state after CNA# or CRDY# is asserted.
CRDY#
NENE# may change its state after CNA# or CRDY# is asserted.
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