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HARDWARE REFERENCE
Triggering a local-to-PCI doorbell interrupt generates a PCI interrupt to the host system. Since a PCI
interrupt from the PCI-SDK Platform can be generated by any of several events, the host system should
poll the Interrupt Control and Status Register (E8H) on the PCI 9060 to determine the cause of the
interrupt. Once a doorbell interrupt is identified, the host system can identify and clear the interrupt by
reading the Local-to-PCI Doorbell Register (E4H), and setting any bit positions which are asserted.
Clearing a bit position which is set, indicating an active interrupt, does not clear the interrupt. If one or
more bits in the doorbell register remain set, the interrupt to the host processor remains asserted. For
local-to-PCI doorbell interrupts to function, PCI interrupts must be enabled and routed on the host
processor, and an appropriate interrupt service routine connected in software.
3.12.7
DMA Programming
Two DMA channels are included on the PCI 9060 to facilitate rapid data transfer across the PCI bus.
Programming is identical for either DMA channel; however, channel 0 contains a 64-byte deep FIFO,
intended for high speed data transfer, and channel 1 contains a 32-byte FIFO, which can be used for
slower data or command transfer. The two channels can operate concurrently, and are both bidirectional.
In addition, both channels support chaining and non-chaining operation. The DMA controllers can be
programmed to interrupt the i960 processor when they complete a task.
3.12.7.1
DMA Non-Chaining Mode
When a DMA channel is operated in non-chaining mode, the local processor programs the Mode, PCI
Address, Local Address, Transfer Size, and Descriptor registers for the DMA channel in question, and
then sets the Command/Status Register to begin the transfer. The DMA transfers the number of bytes
programmed in the DMA Transfer Size Register and, when the operation completes, generates a local
interrupt if the PCI 9060 is programmed to do so.
The PCI and Local Address registers should be programmed with the PCI and local addresses for the
transfer. These registers do not determine transfer direction. Addresses programmed into these registers
may be unaligned. The DMA Transfer Size Register must be set to the number of bytes to be trans-
ferred. Only the lower 23 bits of this register are used; therefore, 8 Mbytes is the maximum transfer size
that can be performed in one operation.
DMA channel functionality is controlled by programming the Mode and Descriptor register bits. The
Mode Register must be programmed with READY inputs enabled and BTERM inputs disabled for the
DMA to operate properly on the PCI-SDK Platform. Burst mode should be enabled to speed transfers.
If the Interrupt on End bit is set, the PCI 9060 generates a local interrupt to the processor when the
DMA transfer completes. The Chaining bit determines whether the DMA operates in chaining or non-
chaining mode, and should be clear for non-chaining transfers. All other values in this register can retain
their default settings.
In non-chaining mode, the Descriptor Pointer Register serves only to indicate the direction of the DMA
transfer. Set this bit for transfers from the local bus to the PCI bus, and clear it for PCI-to-local transfers.
Other bits in this register can be cleared.
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