Transmit Interrupt Generation And Flag Set Timing - Fujitsu MB90335 Series Hardware Manual

CHAPTER 18 UART
18.5 UART Interrupt
18.5.2

Transmit Interrupt Generation and Flag Set Timing

An interrupt during transmission is generated when serial output data register 0, 1
(SODR0, SODR1) becomes empty, or ready to accommodate the next data to transmit.
■ Transmit Interrupt Generation and Flag Set Timing
The sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1" in the state that the sending data that is
written to the serial output data registers 0, 1 (SODR0, SODR1) is transferred to the sending shift register,
the subsequent data goes into the readable state. When the subsequent data is written to the serial output
data registers 0, 1 (SODR0, SODR1), the sending data empty flag bit (SSR0, SSR1: TDRE) is cleared to
"0".
Figure 18.5-2 shows the timing of sending operation and the set of flags.
Figure 18.5-2 Timing of Sending Operation and the Set of Flags
[Operation mode 0, 1]
SODR0, SODR1 write
TDRE
SOT0, SOT1 output
[Operation mode 2]
SODR0, SODR1 write
TDRE
SOT0, SOT1 output
ST : Start bit
D0 to D7 : Data bit
SP : Stop bit
A/D : Address/Data selection bit
408
Transfer interrupt generation
ST D0 D1 D2 D3 D4
Transfer interrupt generation
D0 D1 D2 D3 D4
FUJITSU MICROELECTRONICS LIMITED
Transfer interrupt generation
SP
D5 D6 D7
A/D
Transfer interrupt generation
D5 D6 D7 D0 D1 D2 D3 D4
MB90335 Series
ST D0 D1 D2
SP
D5 D6 D7
CM44-10137-6E
D3