Working With Ecc - Altera Nios II User Manual

Chapter 3: Programming Model

Working with ECC

Normally, a wrctl instruction flushes the pipeline to guarantee that any side effects of
writing control registers take effect immediately after the wrctl instruction completes
execution. However, wrctl instructions to the mpubase and mpuacc control registers do
not automatically flush the pipeline. Instead, system software is responsible for
flushing the pipeline as needed (either by using a flushp instruction or a wrctl
instruction to a register that does flush the pipeline). Because a context switch
typically requires reprogramming the MPU regions for the new thread, flushing the
pipeline on each wrctl instruction would create unnecessary overhead.
MPU Initialization
Your system software must provide a data structure that contains the region
information described in
data structure ideally contains two 32-bit values that correspond to the mpubase and
mpuacc register formats.
The MPU is disabled on system reset. Before enabling the MPU, Altera recommends
initializing all MPU regions. Enable desired instruction and data regions by writing
each region's attributes to the mpubase and mpuacc registers as described in
Region Read and Write Operations" on page
regions. When using region size, clear mpuacc.MASK to zero. When using limit, set the
mpubase.BASE to a nonzero value and clear mpuacc.LIMIT to zero.
1
You must enable at least one instruction and one data region, otherwise unpredictable
behavior might occur.
To perform a context switch, use a wrctl to write a zero to the PE field of the config
register to disable the MPU, define all MPU regions from the new thread's data
structure, and then use another wrctl to write a one to config.PE to enable the MPU.
Define each region using the pair of wrctl instructions described in
Read and Write Operations" on page
sequence until all desired regions are defined.
Debugger Access
The debugger can access all MPU-related control registers using the normal wrctl and
rdctl instructions. During debugging, the Nios II ignores the MPU, effectively
temporarily disabling it.
Working with ECC
Enabling ECC
The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II
RAM blocks to avoid spurious ECC errors.
The Nios II processor executes the INITI instruction on each cache line, which
initializes the instruction cache RAM. The RAM does not require special initialization
because any detected ECC errors are ignored if the line is invalid; the line is invalid
after INITI instructions initialize the tag RAM.
February 2014 Altera Corporation
"Memory Regions" on page 3–8
3–28. You must also disable unused
3–28. Repeat this dual wrctl instruction
for each active thread. The
"MPU
"MPU Region
Nios II Processor Reference Handbook
3–29