Altera Nios II User Manual page 22

2–6
Table 2–2. Hardware Conformance with IEEE 754-1985 and IEEE 754-2008 Floating-Point Standard (Part 2 of 2)
Feature
Round to nearest
Round toward zero
Rounding
Round toward
Modes (1)
+infinity
Round toward
–infinity
Quiet
NaN
Signaling
Subnormal
(denormalized)
numbers
Software
exceptions
Status flags
Note to Table 2–2:
(1) The Floating Point Hardware 2 component also supports faithful rounding, which is not an IEEE 754-defined rounding mode. Faithful rounding
rounds results to either the upper or lower nearest single-precision numbers. Therefore, the result produced is one of two possible values and
the choice between the two is not defined. The maximum error of faithful rounding is 1 unit in the last place (ulp). Errors may not be evenly
distributed.
(2) This operation is not fully compliant with IEEE 754-2008.
Floating Point Custom Instruction 2 Component
You can add floating-point custom instructions to any Nios II processor design. The
floating-point division hardware requires more resources than the other instructions.
The Floating Point Hardware 2 component supports the following single-precision
floating-point operations:
■ Add
Subtract
■
Nios II Processor Reference Handbook
Floating-Point Hardware
Implementation with IEEE 754-1985
Implemented
Not implemented
Not implemented
Not implemented
Implemented
Not implemented
Subnormal operands are treated as zero.
The floating-point custom instructions
do not generate subnormal numbers.
Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Chapter 2: Processor Architecture
Arithmetic Logic Unit
Floating-Point Hardware 2
Implementation with IEEE 754-2008
Implemented (roundTiesToAway mode)
Implemented (truncation mode)
Not implemented
Not implemented
No distinction is made between
signaling and quiet NaNs as input
operands. A result that produces a NaN
may produce either a signaling or quiet
NaN. (2)
The comparison, minimum,
■
maximum, negate, and absolute
operations support subnormal
numbers.
The add, subtract, multiply, divide,
■
square root, and float to integer
operations do NOT support
subnormal numbers. Subnormal
operands are treated as signed zero.
The floating-point custom
instructions do not generate
subnormal numbers. (2)
The integer to float operation cannot
■
create subnormal numbers.
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
table. (2)
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
table. (2)
February 2014 Altera Corporation