Memory Management - Altera Nios II User Manual

Chapter 3: Programming Model
Memory Management Unit
1
The Altera HAL and HAL-based real-time operating systems do not support the
MMU.
If your system needs memory protection, but not virtual memory management, refer
to Memory Protection Unit section.

Memory Management

Memory management comprises two key functions:
■ Virtual addressing—Mapping a virtual memory space into a physical memory
space
■ Memory protection—Allowing access only to certain memory under certain
conditions
Virtual Addressing
A virtual address is the address that software uses. A physical address is the address
which the hardware outputs on the address lines of the Avalon
MMU divides virtual memory into 4-KB pages and physical memory into 4-KB
frames.
The MMU contains a hardware translation lookaside buffer (TLB). The operating
system is responsible for creating and maintaining a page table (or equivalent data
structures) in memory. The hardware TLB acts as a software managed cache for the
page table. The MMU does not perform any operations on the page table, such as
hardware table walks. Therefore the operating system is free to implement its page
table in any appropriate manner.
There is a 20 bit virtual page number (VPN) and a 12 bit page offset.
Table 3–1. MMU Virtual Address Fields
31 30 29 28 27 26 25
As input, the TLB takes a VPN plus a process identifier (to guarantee uniqueness). As
output, the TLB provides the corresponding physical frame number (PFN).
Distinct processes can use the same virtual address space. The process identifier,
concatenated with the virtual address, distinguishes identical virtual addresses in
separate processes. To determine the physical address, the Nios II MMU translates a
VPN to a PFN and then concatenates the PFN with the page offset. The bits in the
page offset are not translated.
Memory Protection
The Nios II MMU maintains read, write, and execute permissions for each page. The
TLB provides the permission information when translating a VPN. The operating
system can control whether or not each process is allowed to read data from, write
data to, or execute instructions on each particular page. The MMU also controls
whether accesses to each data page are cacheable or uncacheable by default.
February 2014 Altera Corporation
24 23 22 21 20 19 18 17
Virtual Page Number
16 15 14 13 12 11 10 9
®
bus. The Nios II
8 7 6 5 4 3 2 1
Page Offset
Nios II Processor Reference Handbook
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