Altera Nios II User Manual page 44

3–4
Whenever an instruction attempts to access a page that either has no TLB mapping, or
lacks the appropriate permissions, the MMU generates an exception. The Nios II
processor's precise exceptions enable the system software to update the TLB, and then
re-execute the instruction if desired.
Address Space and Memory Partitions
The MMU provides a 4-GB virtual address space, and is capable of addressing up to
4 GB of physical memory.
1
The amount of actual physical memory, determined by the configuration of your
hardware system, might be less than the available 4 GB of physical address space.
Virtual Memory Address Space
The 4-GB virtual memory space is divided into partitions. The upper 2 GB of memory
is reserved for the operating system and the lower 2 GB is reserved for user processes.
Table 3–2. Virtual Memory Partitions
Partition Virtual Address Range
I/O (1)
0xE0000000–0xFFFFFFFF
Kernel (1)
0xC0000000–0xDFFFFFFF
Kernel MMU (1)
0x80000000–0xBFFFFFFF
User
0x00000000–0x7FFFFFFF
Note to Table 3–2:
(1) Supervisor-only partition
Each partition has a specific size, purpose, and relationship to the TLB:
■ The 512-MB I/O partition provides access to peripherals.
■ The 512-MB kernel partition provides space for the operating system kernel.
The 1-GB kernel MMU partition is used by the TLB miss handler and kernel
■
processes.
■ The 2-GB user partition is used by application processes.
I/O and kernel partitions bypass the TLB. The kernel MMU and user partitions use
the TLB. If all software runs in the kernel partition, the MMU is effectively disabled.
Nios II Processor Reference Handbook
Used By Memory Access
Operating
Bypasses TLB
system
Operating
Bypasses TLB
system
Operating
Uses TLB
system
User
Uses TLB
processes
Chapter 3: Programming Model
Memory Management Unit
User Mode Default Data
Access Cacheability
No Disabled
No Enabled
No Set by TLB
Set by TLB Set by TLB
February 2014 Altera Corporation