Altera Nios II User Manual page 65

Chapter 3: Programming Model
Registers
The WR Flag
Setting the WR flag signifies that an MPU region write operation should be performed
when a wrctl instruction is issued to the mpuacc register. Refer to the MPU Region
Read and Write Operations section for more information. The WR flag always returns 0
when read by a rdctl instruction.
1
Setting both the RD and WR flags to one results in undefined behavior.
The eccinj Register
The eccinj register injects 1 and 2 bit errors to the Nios II processor's internal RAM
blocks that support ECC. Injecting errors allows the software to test the ECC error
exception handling code. The error(s) are injected in the data bits, not the parity bits.
The eccinj register is only available when ECC is present.
Table 3–31. eccinj Control Register Fields
31 30 29 28 27 26 25 24
Software writes 0x1 to inject a 1 bit ECC error or 0x2 to inject a 2-bit ECC error to the
RAM field. Hardware sets the value of the inject field to 0x0 after the error injection
has occurred.
Table 3–32. eccinj Control Register Field Descriptions
Field
Inject an ECC error in the register file's RAM.
RF
Inject an ECC error in the instruction cache RAM.
ICTAG
Inject an ECC error in the instruction cache data RAM.
ICDAT
Inject an ECC error in the MMU TLB RAM. Errors are injected in the
TLB
tag portion of the VPN field.
f
Refer to
are injected.
Shadow Register Sets
The Nios II processor can optionally have one or more shadow register sets. A
shadow register set is a complete alternate set of Nios II general-purpose registers,
which can be used to maintain a separate runtime context for an interrupt service
routine (ISR).
When shadow register sets are implemented, status.CRS indicates the register set
currently in use. A Nios II core can have up to 63 shadow register sets. If n is the
configured number of shadow register sets, the shadow register sets are numbered
from 1 to n. Register set 0 is the normal register set.
A shadow register set behaves precisely the same as the normal register set. The
register set currently in use can only be determined by examining status.CRS.
February 2014 Altera Corporation
23 22 21 20 19 18 17 16
Reserved
Description
"Working with ECC" on page 3–29
15 14 13 12 11 10 9 8
Reserved
TLB
Access
Read/Write
Read/Write
Read/Write
Read/Write
for more information about when errors
3–25
7 6 5 4 3 2 1
ICDAT ICTAG RF
Reset Available
0 Only with ECC
0 Only with ECC
0 Only with ECC
0 Only with ECC
Nios II Processor Reference Handbook
0