Altera Nios II User Manual page 28

2–12
f
For details that affect programming issues, refer to the
the Nios II Processor Reference Handbook.
Figure 2–2. Nios II Memory and I/O Organization
Nios II Processor Core
Instruction
Program
Counter
General
Purpose
Register
File
Instruction and Data Buses
The Nios II architecture supports separate instruction and data buses, classifying it as
a Harvard architecture. Both the instruction and data buses are implemented as
Avalon-MM master ports that adhere to the Avalon-MM interface specification. The
data master port connects to both memory and peripheral components, while the
instruction master port connects only to memory components.
f
Refer to the
Nios II Processor Reference Handbook
Bus
Selector
MPU Instruction Regions
Logic
MMU
Translation
Lookaside Buffer
Data
Cache
Bypass
Logic
Data
Bus
MPU Data Regions
Selector
Logic
Avalon Interface Specifications
Tightly Coupled
M Instruction
Memory 1
Tightly Coupled
M Instruction
Memory N
Instruction
M
Cache
Data
Cache
M
Tightly Coupled
M
Data
Memory 1
Tightly Coupled
Data
M
Memory N
Avalon Master Port
M
Avalon Slave Port
S
for details of the Avalon-MM interface.
Chapter 2: Processor Architecture
Memory and I/O Organization
Programming Model chapter of
Avalon System
Interconnect
Fabric
S
Memory
Slave
S
Peripheral
February 2014 Altera Corporation