Altera Nios II User Manual page 113

Chapter 4: Instantiating the Nios II Processor
Advanced Features Tab
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■ Division error—Division error detection is only available for the Nios II/f core,
and only then when Hardware divide on the Core Nios II tab is on. When divide
instructions are not supported by hardware, the Division error setting is disabled.
When Division error is on, the processor generates a division error exception
when it detects divide instructions that produce a result that cannot be represented
in the destination register. This only happens in the following two cases:
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■
■ Misaligned memory access—Misaligned memory access detection is only
available for the Nios II/f core. When Misaligned memory access is on, the
processor checks for misaligned memory accesses.
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There are two misaligned memory address exceptions:
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Extra exception information—When Extra exception information is on, nonbreak
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exceptions store a code in the CAUSE field of the exception control register to
indicate the cause of the exception.
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Your exception handler can use this code to quickly determine the proper action to
take, rather than have to determine the cause of an exception through instruction
decoding. Additionally, some exceptions also store the instruction or data address
associated with the exception in the badaddr register.
February 2014 Altera Corporation
When your system contains an MMU or MPU, the processor automatically
generates illegal instruction exceptions. Therefore, the Illegal instruction
setting is always disabled when the Core Nios II tab Include MMU or
Include MPU are on.
Divide by zero
Divide overflow—A signed division that divides the largest negative number
-2147483648 (0x80000000) by -1 (0xffffffff).
When your system contains an MMU or MPU, the processor automatically
generates misaligned memory access exceptions. Therefore, the Misaligned
memory access check box is always disabled when Include MMU or
Include MPU on the Core Nios II tab are on.
Misaligned data address—Data addresses of load and store instructions are
checked for misalignment. A data address is considered misaligned if the byte
address is not a multiple of the data width of the load or store instruction (4
bytes for word, 2 bytes for half-word). Byte load and store instructions are
always aligned so never generate a misaligned data address exception.
Misaligned destination address—Destination instruction addresses of br,
callr, jmp, ret, eret, and bret instructions are checked for misalignment. A
destination instruction address is considered misaligned if the target byte
address of the instruction is not a multiple of four.
When your system contains an MMU or MPU, the processor automatically
generates extra exception information. Therefore, the Extra exception
information setting is always disabled when the Core Nios II tab Include
MMU or Include MPU are on.
Nios II Processor Reference Handbook
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