Altera Nios II User Manual page 147

Chapter 5: Nios II Core Implementation Details
Nios II/e Core
The Nios II/e core employs dedicated shift circuitry to perform shift and rotate
operations. The dedicated shift circuitry achieves one-bit-per-cycle shift and rotate
operations.
Memory Access
The Nios II/e core does not provide instruction cache or data cache. All memory and
peripheral accesses generate an Avalon-MM transfer. The Nios II/e core can address
up to 2 GB of external memory. The Nios II architecture reserves the most-significant
bit of data addresses for the bit-31 cache bypass method. In the Nios II/e core, bit 31 is
always zero.
f
For information regarding data cache bypass methods, refer to the
Architecture
Instruction Execution Stages
This section provides an overview of the pipeline behavior as a means of estimating
assembly execution time. Most application programmers never need to analyze the
performance of individual instructions.
Instruction Performance
The Nios II/e core dispatches a single instruction at a time, and the processor waits
for an instruction to complete before fetching and dispatching the next instruction.
Because each instruction completes before the next instruction is dispatched, branch
prediction is not necessary. This greatly simplifies the consideration of processor
stalls. Maximum performance is one instruction per six clock cycles. To achieve six
cycles, the Avalon-MM instruction master port must fetch an instruction in one clock
cycle. A stall on the Avalon-MM instruction master port directly extends the execution
time of the instruction.
Table 5–17. Instruction Execution Performance for Nios II/e Core
Normal ALU instructions (e.g., add, cmplt)
All branch, jmp, jmpi, ret, call, callr
trap, break, eret, bret,
flushp, wrctl, rdctl,
unimplemented
All load word
All load halfword
All load byte
All store
All shift, all rotate
All other instructions
Combinatorial custom instructions
Multicycle custom instructions
February 2014 Altera Corporation
chapter of the Nios II Processor Reference Handbook.
Instruction Cycles
6
6
6
6 + Duration of Avalon-MM read transfer
9 + Duration of Avalon-MM read transfer
10 + Duration of Avalon-MM read transfer
6 + Duration of Avalon-MM write transfer
7 to 38
6
6
6
Nios II Processor Reference Handbook
5–21
Processor