Tlb Organization - Altera Nios II User Manual

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TLB Organization

A TLB functions as a cache for the operating system's page table. In Nios II processors
with an MMU, one main TLB is shared by instruction and data accesses. The TLB is
stored in on-chip RAM and handles translations for instruction fetches and
instructions that perform data accesses.
The TLB is organized as an n-way set-associative cache. The software specifies the
way (set) when loading a new entry.
1
You can configure the number of TLB entries and the number of ways (set
associativity) of the TLB with the Nios II Processor parameter editor in Qsys. By
default, the TLB is a 16-way cache. The default number of entries depends on the
target device, as follows:
■
■
The operating system software is responsible for guaranteeing that multiple TLB
entries do not map the same virtual address. The hardware behavior is undefined
when multiple entries map the same virtual address.
Each TLB entry consists of a tag and data portion. This is analogous to the tag and
data portion of instruction and data caches.
f
Refer to the
Handbook for information about instruction and data caches.
The tag portion of a TLB entry contains information used when matching a virtual
address to a TLB entry.
Table 3–3. TLB Tag Portion Contents
Field Name
VPN
PID
G
Nios II Processor Reference Handbook
® ®
Cyclone II, Stratix II, Stratix II GX—128 entries, requiring one M4K RAM
Cyclone III, Stratix III, Stratix IV—256 entries, requiring one M9K RAM
For more information, refer to the
the Nios II Processor Reference Handbook.
Nios II Core Implementation Details
VPN is the virtual page number field. This field is compared with the top 20 bits of
the virtual address.
PID is the process identifier field. This field is compared with the value of the
current process identifier stored in the tlbmisc control register, effectively
extending the virtual address. The field size is configurable in the Nios_II
Processor parameter editor, and can be between 8 and 14 bits.
G is the global flag. When G = 1, the PID is ignored in the TLB lookup.
Chapter 3: Programming Model
Instantiating the Nios II Processor
chapter of the Nios II Processor Reference
Description
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Memory Management Unit
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