Altera Nios II User Manual page 47

Chapter 3: Programming Model
Memory Management Unit
The TLB data portion determines how to translate a matching virtual address to a
physical address.
Table 3–4. TLB Data Portion Contents
Field Name
PFN
C
R
W
X
1
Because there is no "valid bit" in the TLB entry, the operating system software
invalidates the TLB by writing unique VPN values from the I/O partition of virtual
addresses into each TLB entry.
TLB Lookups
A TLB lookup attempts to convert a virtual address (VADDR) to a physical address
(PADDR).
Example 3–1. TLB Lookup Algorithm for Instruction Fetches
if (VPN match && (G == 1 || PID match))
else
Example 3–2. TLB Lookup Algorithm for Data Access Operations
if (VPN match && (G == 1 || PID match))
else
f
Refer to
exceptions.
February 2014 Altera Corporation
PFN is the physical frame number field. This field specifies the upper bits of the
physical address. The size of this field depends on the range of physical addresses
present in the system. The maximum size is 20 bits.
C is the cacheable flag. Determines the default data cacheability of a page. Can be
overridden for data accesses using I/O load and store family of Nios II instructions.
R is the readable flag. Allows load instructions to read a page.
W is the writable flag. Allows store instructions to write a page.
X is the executable flag. Allows instruction fetches from a page.
if (X == 1)
PADDR = concat(PFN, VADDR[11:0])
else
take TLB permission violation exception
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
if ((load && R == 1) || (store && W == 1) || flushda)
PADDR = concatenate(PFN, VADDR[11:0])
else
take TLB permission violation exception
if (EH bit of status register == 1)
take double TLB miss exception
else
take fast TLB miss exception
"Instruction-Related Exceptions" on page 3–40
Description
for information about TLB
Nios II Processor Reference Handbook
3–7