Altera Nios II User Manual page 176

7–18
Each PLT entry appears as shown in
Example 7–18. PLT Entry
.PLTn:
orhi
ldw
jmp
Example 7–19
data area for a relative jump.
Example 7–19. PLT Entry Near Small Data Area
.PLTn:
ldw
jmp
Example 7–20. Initial PLT Entry
res_0:
br
...
.PLTresolve:
orhi
addi
sub
orhi
ldw
ldw
jmp
In front of the initial PLT entry, a series of branches start of the initial entry (the nextpc
instruction). There is one branch for each PLT entry, labelled res_0 through res_N. The
last several branches may be replaced by nop instructions to improve performance.
The link editor arranges for the Nth PLT entry to point to the Nth branch; res_N –
res_0 is four times the index into the .rela.plt section for the corresponding
R_JUMP_SLOT relocation.
The dynamic linker initializes GOT[1] to a unique identifier for each library and
GOT[2] to the address of the runtime resolver routine. In order for the two loads in
.PLTresolve to share the same %hiadj, _GLOBAL_OFFSET_TABLE_ must be aligned to a
16-byte boundary.
The runtime resolver receives the original function arguments in r4 through r7, the
shared library identifier from GOT[1] in r14, and the relocation index times four in
r15. The resolver updates the corresponding PLT GOT entry so that the PLT entry
transfers control directly to the target in the future, and then transfers control to the
target.
Nios II Processor Reference Handbook
r15, r0, %hiadj(plt_got_slot_address)
r15, %lo(plt_got_slot_address)(r15)
r15
shows the PLT entry when the PLT GOT is close enough to the small
r15, %gprel(plt_got_slot_address)(gp)
r15
.PLTresolve
r14, r0, %hiadj(res_0)
r14, r14, %lo(res_0)
r15, r15, r14
r13, %hiadj(_GLOBAL_OFFSET_TABLE_)
r14, %lo(_GLOBAL_OFFSET_TABLE_+4)(r13)
r13, %lo(_GLOBAL_OFFSET_TABLE_+8)(r13)
r13
Chapter 7: Application Binary Interface
Example 7–18.
February 2014 Altera Corporation
ABI for Linux Systems