Altera Nios II User Manual page 110

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The following sections describe the configuration settings available.
Instruction Master Settings
The Instruction Master parameters provide the following options for the Nios II/f
and Nios II/s cores:
Instruction cache—Specifies the size of the instruction cache. Valid sizes are from
■
512 bytes to 64 KBytes, or None.
Choosing None disables the instruction cache, which also removes the
Avalon-MM instruction master port from the Nios II processor. In this case, you
must include a tightly-coupled instruction memory.
■ Burst transfers —The Nios II processor can fill its instruction cache lines using
burst transfers. Usually you enable bursts on the processor's instruction master
when instructions are stored in DRAM, and disable bursts when instructions are
stored in SRAM.
Bursting to DRAM typically improves memory bandwidth, but might consume
additional FPGA resources. Be aware that when bursts are enabled, accesses to
slaves might go through additional hardware (called burst adapters) which might
decrease your f
When the Nios II processor transfers execution to the first word of a cache line, the
processor fills the line by executing a sequence of word transfers that have
ascending addresses, such as 0, 4, 8, 12, 16, 20, 24, 28.
However, when the Nios II processor transfers execution to an instruction that is
not the first word of a cache line, the processor fetches the required (or "critical")
instruction first, and then fills the rest of the cache line. The addresses of a burst
increase until the last word of the cache line is filled, and then continue with the
first word of the cache line. For example, with a 32-byte cache line, transferring
control to address 8 results in a burst with the following address sequence: 8, 12,
16, 20, 24, 28, 0, 4.
Data cache victim buffer implementation—Specifies whether to use RAM or
■
registers. The data cache victim buffer temporarily holds a dirty cache line while
the data is written back to external memory.
■ Number of tightly coupled instruction master port(s) (Include tightly coupled
instruction master port(s))—Specifies one to four tightly-coupled instruction
master ports for the Nios II processor. In Qsys, select the number from the
Number of tightly coupled instruction master port(s) list. Tightly-coupled
memory ports appear on the connection panel of the Nios II processor on the Qsys
System Contents tab. You must connect each port to exactly one memory
component in the system.
Data Master Settings
The Data Master parameters provide the following options for the Nios II/f core:
■
Nios II Processor Reference Handbook
.
MAX
Omit data master port—Removes the Avalon-MM data master port from the
Nios II processor. The port is only successfully removed when Data cache is set
to None and Number of tightly coupled data master port(s) is greater than
zero.
Chapter 4: Instantiating the Nios II Processor
Caches and Memory Interfaces Tab
February 2014 Altera Corporation