Altera Nios II User Manual page 154

6–4
Table 6–3. Nios II/f Core Revisions (Part 2 of 3)
Version Release Date
8.0 May 2008
7.2 October 2007
7.1 May 2007
7.0 March 2007
6.1 November 2006
6.0 May 2006
5.1 SP1 January 2006
5.1 October 2005
5.0 May 2005
1.1 December 2004
Nios II Processor Reference Handbook
Implemented the optional MMU.
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Implemented the optional MPU.
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Implemented advanced exception checking.
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Implemented the initda instruction.
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Implemented the jmpi instruction.
No changes.
No changes.
No changes.
Cycle count for flushi and initi instructions changes from 1 to 4 cycles.
Bug Fix:
Back-to-back store instructions can cause memory corruption to the stored data.
If the first store is not to the last word of a cache line and the second store is to the
last word of the line, memory corruption occurs.
No changes.
Added optional tightly-coupled memory ports. Designers can add zero to four
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tightly-coupled instruction master ports, and zero to four tightly-coupled data
master ports.
Made the data cache line size configurable. Designers can configure the data
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cache with the following line sizes: 4, 16, or 32 bytes. Previously, the data
cache line size was fixed at 4 bytes.
Made instruction and data caches optional (previously, cache memories were
■
always present). If the instruction cache is not present, the Nios II core does
not have an instruction master port, and must use a tightly-coupled instruction
memory.
Support for HardCopy devices (previous versions required a workaround to
■
support HardCopy devices).
Added user-configurable options affecting multiply and shift operations. Now
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designers can choose one of three options:
(1) Use embedded multiplier resources available in the target device family
(previously available).
(2) Use logic elements to implement multiply and shift hardware (new option).
(3) Omit multiply hardware. Shift operations take one cycle per bit shifted;
multiply operations are emulated in software (new option).
Added cpuid control register.
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Bug Fix:
■
Interrupts that were disabled by wrctl ienable remained enabled for one
clock cycle following the wrctl instruction. Now the instruction following such
a wrctl cannot be interrupted.
Chapter 6: Nios II Processor Revision History
Notes
February 2014 Altera Corporation
Core Revisions