Altera Nios II User Manual page 80

3–40
1
Although shadow register sets can be implemented in any Nios II/f processor, the
internal interrupt controller does not have features to take advantage of it as external
interrupt controllers do.
Figure 3–2. Relationship Between ienable, ipending, PIE and Hardware Interrupts
Instruction-Related Exceptions
Instruction-related exceptions occur during execution of Nios II instructions. When
they occur, the processor perform the steps outlined in
on page
The Nios II processor generates the following instruction-related exceptions:
Trap instruction
■
■ Break instruction
■ Unimplemented instruction
■ Illegal instruction
Supervisor-only instruction
■
■ Supervisor-only instruction address
■ Supervisor-only data address
■ Misaligned data address
Nios II Processor Reference Handbook
31
External hardware
interrupt request
inputs irq[31..0]
31
PIE bit
3–45.
Chapter 3: Programming Model
ienable Register
. . .
ipending Register
. . .
. . .
Generate
Hardware
Interrupt
"Exception Processing Flow"
February 2014 Altera Corporation
Exception Processing
0
0