Altera Nios II User Manual page 55

Chapter 3: Programming Model
Registers
The exception Register
When the extra exception information option is enabled, the Nios II processor
provides information useful to system software for exception processing in the
exception and badaddr registers when an exception occurs. When your system
contains an MMU or MPU, the extra exception information is always enabled. When
no MMU or MPU is present, the Nios II Processor parameter editor gives you the
option to have the processor provide the extra exception information.
For information about controlling the extra exception information option, refer to the
Instantiating the Nios II Processor
Table 3–11. exception Control Register Fields
30 29 28 27 26 25 24
Table 3–12. exception Control Register Field Descriptions
Field
The Nios II processor writes to ECCFTL when it detects a potentially
fatal ECC error. When ECCFTL = 1, the Nios II processor detects an
ECCFTL
ECC register file error. When ECCFTL = 0, another ECC exception
occurred.
CAUSE is written by the Nios II processor when certain exceptions
occur. CAUSE contains a code for the highest-priority exception
occurring at the time. The Cause column in the Nios II Exceptions
CAUSE
(In Decreasing Priority Order table lists the CAUSE field value for
each exception.
CAUSE is not written on a break or an external interrupt.
The pteaddr Register
The pteaddr register contains the virtual address of the operating system's page table
and is only available in systems with an MMU. The pteaddr register layout
accelerates fast TLB miss exception handling.
Table 3–13. pteaddr Control Register Fields
31 30 29 28 27 26 25
PTBASE
Table 3–14. pteaddr Control Register Field Descriptions
Field
PTBASE is the base virtual address of the page table.
PTBASE
VPN is the virtual page number. VPN can be set by both hardware
VPN
and software.
Software writes to the PTBASE field when switching processes. Hardware never writes
to the PTBASE field.
February 2014 Altera Corporation
23 22 21 20 19 18 17
Reserved
Description
24 23 22 21 20 19 18 17
Description
chapter of the Nios II Processor Reference Handbook.
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
VPN
Read/Write
Read/Write
8 7 6 5 4 3 2
CAUSE
Access Reset Available
Read 0 Only with ECC
Only with
extra
Read 0
exception
information
8 7 6 5 4 3 2
Access Reset Available
Only with
0
MMU
Only with
0
MMU
Nios II Processor Reference Handbook
3–15
1 0
Rsvd
1 0
Rsvd