Altera Nios II User Manual page 36

2–20
Hardware Triggers
Hardware triggers activate a debug action based on conditions on the instruction or
data bus during real-time program execution. Triggers can do more than halt
processor execution. For example, a trigger can be used to enable trace data collection
during real-time processor execution.
Hardware trigger conditions are based on either the instruction or data bus. Trigger
conditions on the same bus can be logically ANDed, enabling the JTAG debug
module to trigger, for example, only on write cycles to a specific address.
Table 2–5. Trigger Conditions
Specific address
Specific data value
Read cycle
Write cycle
Armed
Range
When a trigger condition occurs during processor execution, the JTAG debug module
triggers an action, such as halting execution, or starting trace capture. The table below
lists the trigger actions supported by the Nios II JTAG debug module.
Table 2–6. Trigger Actions
Break
External trigger
Trace on
Trace off
Trace sample
Arm
Note to
(1) Only conditions on the data bus can trigger this action.
Armed Triggers
The JTAG debug module provides a two-level trigger capability, called armed
triggers. Armed triggers enable the JTAG debug module to trigger on event B, only
after event A. In this example, event A causes a trigger action that enables the trigger
for event B.
Nios II Processor Reference Handbook
Condition Bus
Data,
Instruction
Data
Data
Data
Data,
Instruction
Data
Action
Halt execution and transfer control to the JTAG debug module.
Assert a trigger signal output. This trigger output can be used, for example,
to trigger an external logic analyzer.
Turn on trace collection.
Turn off trace collection.
(1) Store one sample of the bus to trace buffer.
Enable an armed trigger.
Table 2–6:
Description
Trigger when the bus accesses a specific address.
Trigger when a specific data value appears on the bus.
Trigger on a read bus cycle.
Trigger on a write bus cycle.
Trigger only after an armed trigger event. Refer to the Armed
Triggers section.
Trigger on a range of address values, data values, or both. Refer
to the Triggering on Ranges of Values section.
Description
Chapter 2: Processor Architecture
JTAG Debug Module
February 2014 Altera Corporation