Altera Nios II User Manual page 242

8–62
ldh / ldhio
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31 30 29 28 27 26 25
A
31 30 29 28 27 26 25
A
Nios II Processor Reference Handbook
rB ← σ (Mem16[rA + σ (IMM16)])
ldh rB, byte_offset(rA)
ldhio rB, byte_offset(rA)
ldh r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Loads register rB with the memory halfword located at the effective byte
address, sign extending the 16-bit value to 32 bits. The effective byte address must be halfword
aligned. If the byte address is not a multiple of 2, the operation is undefined.
In processors with a data cache, this instruction may retrieve the desired data from the cache
instead of from memory. Use the ldhio instruction for peripheral I/O. In processors with a data
cache, ldhio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache, ldhio acts like ldh.
For more information on data cache, refer to the
the Nios II Software Developer's Handbook.
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
24 23 22 21 20 19 18 17
B
Instruction format for ldh
24 23 22 21 20 19 18 17
B
Instruction format for ldhio
load halfword from memory or I/O peripheral
Cache and Tightly Coupled Memory
16 15 14 13 12 11 10 9
IMM16
16 15 14 13 12 11 10 9
IMM16
Chapter 8: Instruction Set Reference
Instruction Set Reference
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February 2014 Altera Corporation
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