Altera Nios II User Manual page 75

Chapter 3: Programming Model
Exception Processing
Interrupt Latency
The interrupt controller can mask individual interrupts. Each interrupt can have a
different maximum masked time. The worst-case interrupt latency for interrupt i is
determined by that interrupt's maximum masked time, or by the maximum disabled
time, whichever is greater.
Reset Exceptions
When a processor reset signal is asserted, the Nios II processor performs the following
steps:
1. Sets status.RSIE to 1, and clears all other fields of the status register.
2. Invalidates the instruction cache line associated with the reset vector.
3. Begins executing the reset handler, located at the reset vector.
1
All noninterrupt exception handlers must run in the normal register set.
Clearing the status.PIE field disables maskable interrupts. If the MMU or MPU is
present, clearing the status.U field forces the processor into supervisor mode.
1
Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be taken
while processing a reset exception.
Invalidating the reset cache line guarantees that instruction fetches for reset code
comes from uncached memory.
Aside from the instruction cache line associated with the reset vector, the contents of
the cache memories are indeterminate after reset. To ensure cache coherency after
reset, the reset handler located at the reset vector must immediately initialize the
instruction cache. Next, either the reset handler or a subsequent routine should
proceed to initialize the data cache.
The reset state is undefined for all other system components, including but not
limited to:
■ General-purpose registers, except for zero (r0) in the normal register set, which is
permanently zero.
Control registers, except for status. status.RSIE is reset to 1, and the remaining
■
fields are reset to 0.
■ Instruction and data memory.
■ Cache memory, except for the instruction cache line associated with the reset
vector.
■ Peripherals. Refer to the appropriate peripheral data sheet or specification for reset
conditions.
Custom instruction logic. Refer to the
■
conditions.
■ Nios II C-to-hardware (C2H) acceleration compiler logic.
February 2014 Altera Corporation
Nios II Custom Instruction User Guide
Nios II Processor Reference Handbook
3–35
for reset