Altera Nios II User Manual page 118

4–14
The following sections describe the configuration settings available.
Debug Level Settings
The following debug levels are available in the JTAG Debug Module tab:
No Debugger
■
■ Level 1
■ Level 2
■ Level 3
■ Level 4
The table is a detailed list of the characteristics of each debug level. Different levels
consume different amounts of on-chip resources. Certain Nios II cores have restricted
debug options, and certain options require debug tools provided by MIPS
Technologies or Lauterbach GmbH.
f
For information about debug features available from these third parties, search for
"Nios II" on the MIPS Technologies website (www.mips.com) and the Lauterbach
GmbH website (www.lauterbach.com).
Table 4–7. JTAG Debug Module Levels
Debug Feature
Logic Usage
On-Chip Memory Usage
External I/O Pins Required (2)
JTAG Target Connection
Download Software
Software Breakpoints
Hardware Execution
Breakpoints
Data Triggers
On-Chip Trace
Off-Chip Trace (4)
Notes to Table 4–7:
(1) Level 4 requires the purchase of a software upgrade from MIPS Technologies or Lauterbach.
(2) Not including the dedicated JTAG pins on the Altera FPGA.
(3) An additional license from MIPS Technologies is required to use more than 16 frames.
(4) Off-chip trace requires the purchase of additional hardware from MIPS Technologies or Lauterbach.
Nios II Processor Reference Handbook
No Debug Level 1
0 300—400 LEs
0 Two M4Ks
0 0
No Yes
No Yes
None Unlimited
0 None
0 None
0 None
0 None
Chapter 4: Instantiating the Nios II Processor
Level 2 Level 3
800—900 LEs 2,400—2,700 LEs 3,100—3,700 LEs
Two M4Ks Four M4Ks
0 0
Yes Yes
Yes Yes
Unlimited Unlimited
2 2
2 2
Up to 64-KB
None
frames (3)
None None
February 2014 Altera Corporation
JTAG Debug Module Tab
Level 4 (1)
Four M4Ks
20
Yes
Yes
Unlimited
4
4
Up to 64-KB
frames
128-KB frames