Altera Nios II User Manual page 61

Chapter 3: Programming Model
Registers
Table 3–22. config Control Register Field Descriptions (Part 2 of 2)
Field
ECCEN is the ECC enable bit. When ECCEN = 0, the Nios II processor
ignores all ECC errors. When ECCEN = 1, the Nios II processor
ECCEN
recovers all recoverable ECC errors.
PE is the memory protection enable bit. When PE =1, the MPU is
enabled. When PE = 0, the MPU is disabled. In systems without an
PE
MPU, PE is always zero.
The mpubase Register
The mpubase register works in conjunction with the mpuacc register to set and retrieve
MPU region information and is only available in systems with an MPU.
Table 3–23. mpubase Control Register Fields
31 30 29 28 27 26 25
0
Notes:
(1) This field size is variable. Unused upper bits must be written as zero.
(2) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
.
Table 3–24. mpubase Control Register Field Descriptions
Field
BASE is the base memory address of the region identified by the
BASE
INDEX and D fields.
INDEX is the region index number.
INDEX
D is the region access bit. When D =1, INDEX refers to a data region.
D
When D = 0, INDEX refers to an instruction region.
The BASE field specifies the base address of an MPU region. The 25-bit BASE field
corresponds to bits 6 through 30 of the base address, making the base address always
a multiple of 64 bytes. If the minimum region size set in Qsys at generation time is
larger than 64 bytes, unused low-order bits of the BASE field must be written as zero
and are read as zero. For example, if the minimum region size is 1024 bytes, the four
least-significant bits of the BASE field (bits 6 though 9 of the mpubase register) must be
zero. Similarly, if the Nios II address space is less than 31 bits, unused high-order bits
must also be written as zero and are read as zero.
The INDEX and D fields specify the region information to access when an MPU region
read or write operation is performed. The D field specifies whether the region is a data
region or an instruction region. The INDEX field specifies which of the 32 data or
instruction regions to access. If there are fewer than 32 instruction or 32 data regions,
unused high-order bits must be written as zero and are read as zero.
Refer to the MPU Regoin Read and Write Operations section for more information on
MPU region read and write operations.
February 2014 Altera Corporation
Description
24 23 22 21 20 19 18 17
(2)
BASE
Description
Read/Write
Read/Write
16 15 14 13 12 11 10 9
Read/Write
Read/Write
Read/Write
Access Reset Available
0 Only with ECC
Only with
0
MPU
8 7 6 5 4 3 2
(1)
INDEX
Access Reset Available
Only with
0
MPU
Only with
0
MPU
Only with
0
MPU
Nios II Processor Reference Handbook
3–21
1 0
D