Instruction Set Categories - Altera Nios II User Manual

Chapter 3: Programming Model

Instruction Set Categories

Instruction Set Categories
This section introduces the Nios II instructions categorized by type of operation
performed.
Data Transfer Instructions
The Nios II architecture is a load-store architecture. Load and store instructions
handle all data movement between registers, memory, and peripherals. Memories and
peripherals share a common address space. Some Nios II processor cores use memory
caching and/or write buffering to improve memory bandwidth. The architecture
provides instructions for both cached and uncached accesses.
Table 3–40. Wide Data Transfer Instructions
Instruction
The ldw and stw instructions load and store 32-bit data words from/to memory. The effective address is the
sum of a register's contents and a signed immediate value contained in the instruction. Memory transfers can
ldw
be cached or buffered to improve program performance. This caching and buffering might cause memory
stw
cycles to occur out of order, and caching might suppress some cycles entirely.
Data transfers for I/O peripherals should use ldwio and stwio.
ldwio and stwio instructions load and store 32-bit data words from/to peripherals without caching and
ldwio
buffering. Access cycles for ldwio and stwio instructions are guaranteed to occur in instruction order and
stwio
are never suppressed.
Table 3–41. Narrow Data Transfer Instructions
Instruction
ldb
ldb, ldbu, ldh and ldhu load a byte or half-word from memory to a register. ldb and ldh sign-extend the
ldbu
value to 32 bits, and ldbu and ldhu zero-extend the value to 32 bits.
stb
stb and sth store byte and half-word values, respectively.
ldh
Memory accesses can be cached or buffered to improve performance. To transfer data to I/O peripherals,
ldhu
use the io versions of the instructions, described in the following table cell.
sth
ldbio
ldbuio
stbio
These operations load/store byte and half-word data from/to peripherals without caching or buffering.
ldhio
ldhuio
sthio
February 2014 Altera Corporation
Description
Description
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Nios II Processor Reference Handbook