Altera Nios II User Manual page 142

5–16
Multiply and Divide Performance
The Nios II/s core provides the following hardware multiplier options:
DSP Block—Includes DSP block multipliers available on the target device. This
■
option is available only on Altera FPGAs that have DSP Blocks.
■ Embedded Multipliers—Includes dedicated embedded multipliers available on the
target device. This option is available only on Altera FPGAs that have embedded
multipliers.
■ Logic Elements—Includes hardware multipliers built from logic element (LE)
resources.
■ None—Does not include multiply hardware. In this case, multiply operations are
emulated in software.
The Nios II/s core also provides a hardware divide option that includes LE-based
divide circuitry in the ALU.
Including an ALU option improves the performance of one or more arithmetic
instructions.
1
The performance of the embedded multipliers differ, depending on the target FPGA
family.
Table 5–13. Hardware Multiply and Divide Details for the Nios II/s Core
ALU Option
No hardware multiply or divide
LE-based multiplier
Embedded multiplier on
Stratix II and Stratix III families
Embedded multiplier on
Cyclone II and Cyclone III
families
Hardware divide
Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply option. When
a hardware multiplier is present, the ALU achieves shift and rotate operations in three
or four clock cycles. Otherwise, the ALU includes dedicated shift circuitry that
achieves one-bit-per-cycle shift and rotate performance. Refer to
page 5–19
Nios II Processor Reference Handbook
Hardware Details
Multiply and divide instructions
generate an exception
ALU includes 32 x 4-bit
multiplier
ALU includes 32 x 32-bit
multiplier
ALU includes 32 x 16-bit
multiplier
ALU includes multicycle divide
circuit
for details.
Chapter 5: Nios II Core Implementation Details
Cycles per
Supported Instructions
instruction
– None
11
mul, muli
mul, muli, mulxss, mulxsu,
3
mulxuu
5
mul, muli
4 – 66
div, divu
Table 5–16 on
February 2014 Altera Corporation
Nios II/s Core