Altera Nios II User Manual page 83

Chapter 3: Programming Model
Exception Processing
Misaligned Destination Address
The Nios II processor can check for misaligned destination addresses of the callr,
jmp, ret, eret, bret, and all branch instructions and generate an exception when a
misaligned destination address is encountered. When your system contains an MMU
or MPU, misaligned destination address checking is always on. When no MMU or
MPU is present, you have the option to have the processor check for misaligned
destination addresses.
f
For information about controlling this option, refer to the
Processor
A destination address is considered misaligned if the target byte address of the
instruction is not a multiple of four.
Division Error
The Nios II processor can check for division errors and generate an exception when a
division error is encountered.
f
For information about controlling this option, refer to the
Processor
The division error exception detects divide instructions that produce a quotient that
can't be represented. The two cases are divide by zero and a signed division that
divides the largest negative number -2147483648 (0x80000000) by -1 (0xffffffff).
Division error detection is only available if divide instructions are supported by
hardware.
Fast TLB Miss
Fast TLB miss exceptions are implemented only in Nios II processors that include the
MMU. The MMU has a special exception vector (fast TLB miss), specified with the
Nios II Processor parameter editor in Qsys, specifically to handle TLB miss exceptions
quickly. Whenever the processor cannot find a TLB entry matching the VPN
(optionally extended by a process identifier), the result is a TLB miss exception. At the
time of the exception, the processor first checks status.EH. When status.EH = 0, no
other exception is already in process, so the processor considers the TLB miss a fast
TLB miss, sets status.EH to one, and transfers control to the fast TLB miss exception
handler (rather than to the general exception handler).
There are two kinds of fast TLB miss exceptions:
■ Fast TLB miss (instruction)—Any instruction fetch can cause this exception.
■ Fast TLB miss (data)—Load, store, initda, and flushda instructions can cause this
exception.
The fast TLB miss exception handler can inspect the tlbmisc.D field to determine
which kind of fast TLB miss exception occurred.
February 2014 Altera Corporation
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook.
Instantiating the Nios II
Instantiating the Nios II
Nios II Processor Reference Handbook
3–43