Altera Nios II User Manual page 279

Chapter 8: Instruction Set Reference
Instruction Set Reference
trap
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31 30 29 28 27 26 25
0
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estatus ← status
PIE ← 0
U ← 0
ea ← PC + 4
PC ← exception handler address
trap
trap imm5
trap
Saves the address of the next instruction in register ea, saves the contents of the status
register in estatus, disables interrupts, and transfers execution to the exception handler. The
address of the exception handler is specified with the Nios_II Processor parameter editor in
Qsys.
The 5-bit immediate field imm5 is ignored by the processor, but it can be used by the debugger.
trap with no argument is the same as trap 0.
To return from the exception handler, execute an eret instruction.
Trap
R
IMM5 = Type of breakpoint
24 23 22 21 20 19 18 17
0 0x1d
16 15 14 13 12 11 10 9
0x2d
8 7 6 5 4 3 2
IMM5 0x3a
Nios II Processor Reference Handbook
8–99
trap
1 0