Exception Handling - Altera Nios II User Manual

5–12
Table 5–10. Instruction Execution Performance for Nios II/f Core 4byte/line data cache (Part 2 of 2)
Shift/rotate (with hardware multiply using LE-based multipliers)
Shift/rotate (without hardware multiply present)
All other instructions
Notes to Table 5–10:
(1) Depends on the hardware multiply or divide option. Refer to
(2) In the default Nios II/f configuration, these instructions require four clock cycles. If any of the following options are present, they require five
clock cycles:
■ MMU
MPU
■
Division exception
■
Misaligned load/store address exception
■
Extra exception information
■
EIC port
■
Shadow register sets
■

Exception Handling

The Nios II/f core supports the following exception types:
Hardware interrupts
■
■ Software trap
■ Illegal instruction
■ Unimplemented instruction
Supervisor-only instruction (MMU or MPU only)
■
Supervisor-only instruction address (MMU or MPU only)
■
■ Supervisor-only data address (MMU or MPU only)
■ Misaligned data address
■ Misaligned destination address
Division error
■
■ Fast translation lookaside buffer (TLB) miss (MMU only)
■ Double TLB miss (MMU only)
■ TLB permission violation (MMU only)
■ MPU region violation (MPU only)
External Interrupt Controller Interface
The EIC interface enables you to speed up interrupt handling in a complex system by
adding a custom interrupt controller.
The EIC interface is an Avalon-ST sink with the following input signals:
■
eic_port_valid
■
eic_port_data
Nios II Processor Reference Handbook
Instruction
Table 5–4 on page 5–5
Chapter 5: Nios II Core Implementation Details
Cycles
2
1 to 32
1
for details.
February 2014 Altera Corporation
Nios II/f Core
Penalties
Late result
Late result