Exception Processing - Altera Nios II User Manual

Chapter 3: Programming Model

Exception Processing

■ Use a JMP instruction to jump to an instruction address in the flushed line.
■ The ECC error is injected when writing the tag RAM at the start of the line fill.
Use a RDCTL instruction to ensure that the value of ECCINJ.ICTAG is NOINJ.
■
■ The ECC error triggers after the target of the JMP instruction.
Instruction Cache Data RAM
Use the same procedure as for the instruction cache tag RAM with the following
changes:
■ Access the ECCINJ.ICDAT field instead of ECCINJ.ICTAG.
■ Execute the target of the JMP instruction twice (first to inject the ECC error and
second to be triggered by it).
MMU TLB RAM
Use a WRCTL instruction to set ECCINJ.TLB to INJS or INJD (as desired).
■
■ Use a WRCTL instruction to write a TLB entry. The ECC error is injected at this time
and any associated uTLB entry is flushed.
■ Use a RDCTL instruction to ensure that the value of ECCINJ.TLB is NOINJ.
■ Perform an instruction/data access to cause the hardware to read the TLB entry
(copied into uTLB). The ECC decoder should detect the ECC error at this time.
Alternatively, initiate read the TLB with software (by writing TLBMISC.RD to 1).
If a software read was initiated, set the TLBMISC.EE field to 1 on any instruction
■
after the WRCTL that triggered the event.
Register File RAM Blocks
■ Use a WRCTL instruction to set ECCINJ.RF to INJS or INJD (as desired).
■ Execute any instruction that writes any register except R0.
■ Use a RDCTL instruction to ensure that the value of ECCINJ.RF is NOINJ.
Use an instruction to read the desired register from rA such as OR rd, r0, rx
■
where rx is the register written in the previous step. This action triggers the ECC
error.
■ Use an instruction to read the desired register from rB such as OR rd, rx, r0
where rx is the register written in the previous step.
Exception Processing
Exception processing is the act of responding to an exception, and then returning, if
possible, to the pre-exception execution state.
All Nios II exceptions are precise. Precise exceptions enable the system software to
re-execute the instruction, if desired, after handling the exception.
February 2014 Altera Corporation
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Nios II Processor Reference Handbook