Memory Protection Unit - Altera Nios II User Manual

3–8

Memory Protection Unit

The Nios II processor provides an MPU for operating systems and runtime
environments that desire memory protection but do not require virtual memory
management. For information about memory protection with virtual memory
management, refer to the Memory Management Unit section.
When present and enabled, the MPU monitors all Nios II instruction fetches and data
memory accesses to protect against errant software execution. The MPU is a hardware
facility that system software uses to define memory regions and their associated
access permissions. The MPU triggers an exception if software attempts to access a
memory region in violation of its permissions, allowing you to intervene and handle
the exception as appropriate. The precise exception effectively prevents the illegal
access to memory.
The MPU extends the Nios II processor to support user mode and supervisor mode.
Typically, system software runs in supervisor mode and end-user applications run in
user mode, although all software can run in supervisor mode if desired. System
software defines which MPU regions belong to supervisor mode and which belong to
user mode.
Memory Regions
The MPU contains up to 32 instruction regions and 32 data regions. Each region is
defined by the following attributes:
■ Base address
■ Region type
Region index
■
■ Region size or upper address limit
■ Access permissions
■ Default cacheability (data regions only)
Base Address
The base address specifies the lowest address of the region. The base address is
aligned on a region-sized boundary. For example, a 4-KB region must have a base
address that is a multiple of 4 KB. If the base address is not properly aligned, the
behavior is undefined.
Region Type
Each region is identified as either an instruction region or a data region.
Region Index
Each region has an index ranging from zero to the number of regions of its region type
minus one. Index zero has the highest priority.
Nios II Processor Reference Handbook
Chapter 3: Programming Model
Memory Protection Unit
February 2014 Altera Corporation