Altera Nios II User Manual page 85

Chapter 3: Programming Model
Exception Processing
■ MPU region violation (data)—Load, store, initda, and flushda instructions can
cause this exception.
The general exception handler can inspect the exception.CAUSE field to determine
which kind of MPU region violation exception occurred.
Other Exceptions
The preceding sections describe all of the exception types defined by the Nios II
architecture at the time of publishing. However, some processor implementations
might generate exceptions that do not fall into the categories listed in the preceding
sections. Therefore, a robust exception handler must provide a safe response (such as
issuing a warning) in the event that it cannot identify the cause of an exception.
Exception Processing Flow
Except for the break exception (refer to
section describes how the processor responds to exceptions, including interrupts and
instruction-related exceptions.
f
For details about writing programs to take advantage of exception and interrupt
handling, refer to the
Handbook.
Processing General Exceptions
The general exception handler is a routine that determines the cause of each exception
(including the double TLB miss exception), and then dispatches an exception routine
to respond to the exception. The address of the general exception handler, specified
with the Nios II Processor parameter editor in Qsys, is called the exception vector in
the Nios II Processor parameter editor. At run time this address is fixed, and software
cannot modify it. Programmers do not directly access exception vectors, and can write
programs without awareness of the address.
1
If the EIC interface is present, the general exception handler processes only
noninterrupt exceptions.
The fast TLB miss exception handler only handles the fast TLB miss exception. It is
built for speed to process TLB misses quickly. The fast TLB miss exception handler
address, specified with the Nios II Processor parameter editor in Qsys, is called the
fast TLB miss exception vector in the Nios II Processor parameter editor.
Exception Flow with the EIC Interface
If the EIC interface is present, interrupt processing differs markedly from
noninterrupt exception processing. The EIC interface provides the following
information to the Nios II processor for each interrupt request:
■ RHA—The requested handler address for the interrupt handler assigned to the
requested interrupt.
RRS—The requested register set to be used when the interrupt handler executes. If
■
shadow register sets are not implemented, RRS must always be 0.
February 2014 Altera Corporation
"Processing a Break" on page
Exception Handling chapter of the Nios II Software Developer's
3–45
3–36), this
Nios II Processor Reference Handbook