Altera Nios II User Manual page 139

Chapter 5: Nios II Core Implementation Details
Nios II/f Core
Signals are rising-edge triggered, and synchronized with the Nios II clock input.
The EIC interface presents the following signals to the Nios II processor through the
eic_port_data signal:
Requested handler address (RHA)—The 32-bit address of the interrupt handler
■
associated with the requested interrupt.
■ Requested register set (RRS)—The six-bit number of the register set associated with
the requested interrupt.
■ Requested interrupt level (RIL)—The six-bit interrupt level. If RIL is 0, no interrupt is
requested.
Requested nonmaskable interrupt (RNMI) flag—A one-bit flag indicating whether the
■
interrupt is to be treated as nonmaskable.
Table 5–11. eic_port_data Signal
44
Following Avalon-ST protocol requirements, the EIC interface samples eic_port_data
only when eic_port_valid is asserted (high). When eic_port_valid is not asserted,
the processor latches the previous values of RHA, RRS, RIL and RNMI. To present
new values on eic_port_data, the EIC must transmit a new packet, asserting
eic_port_valid. An EIC can transmit a new packet once per clock cycle.
f
For an example of an EIC implementation, refer to the Vectored Interrupt Controller
chapter in the
ECC
The Nios II/f core has the option to add ECC support for the following Nios II
internal RAM blocks.
Instruction cache
■
■
■ Register file
■
■
■ MMU TLB
■
■
■
February 2014 Altera Corporation
...
RHA
Embedded Peripherals IP User
ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable;
the Nios II processor flushes the cache line and reads from external memory
instead of correcting the ECC error.
1 bit ECC errors are recoverable
2 bit ECC errors are not recoverable and generate ECC exceptions
1 bit ECC errors triggered by hardware reads are recoverable
2 bit ECC errors triggered by hardware reads are not recoverable and generate
ECC exception.
1 or 2 bit ECC errors triggered by software reads to the TLBMISC register do
not trigger an exception, instead, TLBMISC.EE is set to 1. Software must read
this field and invalidate/overwrite the TLB entry.
13 12 ... 7
RRS
Guide.
Nios II Processor Reference Handbook
5–13
6 5 ... 0
RIL