Altera NIOS II Reference Manual
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Altera NIOS II Reference Manual

Stratix ii edition
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Download this manual See also: User Manual
Nios Development Board
Reference Manual, Stratix II Edition
Preliminary Information
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com

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Summary of Contents for Altera NIOS II

  • Page 1 Nios Development Board Reference Manual, Stratix II Edition Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com...
  • Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.

  • Page 3: Table Of Contents

    Contents About this Manual .................. v How to Find Information ......................... v How to Contact Altera ..........................vi Typographic Conventions ........................vii Introduction ..................1 Features Overview ..........................1–1 General Description ..........................1–1 Board Components ................. 5 Component List ............................2–5 Stratix II Device (U60) ...........................
  • Page 4 Connecting the Ethernet Cable ......................C–1 Connecting the LCD Screen ........................ C–2 Obtaining an IP Address ........................C–2 LAN Connection ..........................C–3 DHCP ............................C–3 Static IP Address ........................C–3 Point–to–Point Connections ......................C–4 Browsing to Your Board ........................C–5 Altera Corporation...

  • Page 5: About This Manual

    Bookmarks serve as an additional table of contents. ■ Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. ■ Numerous links, shown in green text, allow you to jump to related information. Altera Corporation July 2005...

  • Page 6: How To Contact Altera

    (1) lit_req@altera.com (1) Non-technical customer (800) 767-3753 (408) 544-7000 service (7:30 a.m. to 5:30 p.m. Pacific Time) FTP site ftp.altera.com ftp.altera.com Note to table: You can also contact your local Altera sales office or sales representative. Altera Corporation July 2005...

  • Page 7: Typographic Conventions

    The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation July 2005...
  • Page 8 Typographic Conventions viii Altera Corporation July 2005...

  • Page 9: Introduction

    FPGA designs that interface with all components on the board. Refer to the Nios II Development Kit, Getting Started User Guide for instructions on setting up the Nios development board and installing Nios II development tools.
  • Page 10 FPGA; if the letters “ES” appear on the label, the device is an engineering sample. For details, refer to the Stratix II FPGA Family Errata Sheet and the documented example designs included in the Nios II Development Kit. 1–2 Altera Corporation...
  • Page 11 When power is applied to the board, on-board logic configures the Stratix II FPGA using hardware configuration data stored in flash Programmed memory. When the device is configured, the Nios II processor design in the FPGA wakes up and begins executing boot code from flash memory. Reference Design The board is factory-programmed with a default reference design.
  • Page 12 Factory-Programmed Reference Design 1–4 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 13: Board Components

    (see Figure 2–1). A complete set of schematics, a physical layout database, and GERBER files for the development board are installed in the Nios II development kit documents directory. Figure 2–1 Table 2–1 on page 2–6 for locations and brief descriptions of all features of the board.
  • Page 14 Mictor connector for debugging Nios II systems using a First Silicon Solutions (FS2) debug probe. JTAG connector Connects to the FPGA allowing hardware configuration from Quartus II software and software debug from the Nios II IDE. JTAG connector Connects to the configuration controller Configuration & Reset...

  • Page 15: Stratix Ii Device (U60)

    Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 2 of 2) Board Designation Name Description CPU Reset button Push-button switch to reboot the Nios II processor configured in the FPGA Factory Config Push-button switch to reconfigure the FPGA with the factory-...
  • Page 16 Controller Device (U3)” on page 2–25. For Stratix II-related documentation including Stratix II pinout data refer to the Altera Stratix II literature page at www.altera.com/ literature/lit- stx2.html. Early shipments of the board had a heat sink mounted on the Stratix II FPGA.

  • Page 17: Push-Button Switches (Sw0 - Sw3)

    Stratix II pin drives logic 1, the corresponding LED turns on. Table 2–4. LED Pin Out Table Stratix II Pin AD26 AD25 AC25 AC24 AB24 AB23 AB26 AB25 Altera Corporation 2–9 July 2005 Nios Development Board Reference Manual, Stratix II Edition...

  • Page 18: Seven-Segment Leds (U8 & U9)

    SRAM devices. They are connected to the Stratix II device so they can be (U35 & U36) used by a Nios II embedded processor as general-purpose memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem.

  • Page 19: Flash Memory (U5)

    “Configuration Controller Device (U3)” on page 2–25 for related information. A Nios II processor design in the FPGA can identify the 16 Mbyte flash memory in its address space, and can program new data (either new Stratix II configuration data, Nios II embedded processor software, or both) into flash memory.
  • Page 20 The SDRAM device pins are connected to the Stratix II device (see Table 2–5). An SDRAM controller peripheral is included with the Nios II development kit, allowing a Nios II processor to view the SDRAM device as a large, linearly-addressable memory. Table 2–5. SDRAM (U57) Pin Table (Part 1 of 2)
  • Page 21 AF24 DQ27 AE24 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N AE17 CAS_N AE16 AE20 CS_N AE19 WE_N AE18 AF12 Refer to www.micron.com for detailed information. Altera Corporation 2–13 July 2005 Nios Development Board Reference Manual, Stratix II Edition...

  • Page 22: Serial Port Connectors (J19 & J27)

    The LAN91C111 (U4) is a mixed signal analog/digital device that implements protocols at 10 Mbps and 100 Mbps. The control pins of U4 MAC/PHY (U4) are connected to the Stratix II device so that Nios II systems can access Ethernet via the RJ-45 connector (RJ1).See Figure 2–4 on page 2–14.

  • Page 23: Expansion Prototype Connectors (Proto1 & Proto2)

    ● ■ A buffered, zero-skew copy of the on-board oscillator output from ■ A buffered, zero-skew copy of the Stratix II phase-locked loop (PLL) output from U60. Altera Corporation 2–15 July 2005 Nios Development Board Reference Manual, Stratix II Edition...
  • Page 24 CompactFlash connector (CON3). Designs may use either the PROTO1 connector or the CompactFlash connector. Refer to the Altera web site for a list of available expansion daughter cards that can be used with the Nios development board at www.altera.com/devkits.
  • Page 25 Figure 2–8. PROTO1 Pin Information - J11, J12 & J13 Note to Figure 2–8 Unregulated voltage from DC power supply Clk from board oscillator Clk from FPGA via buffer Clk output from protocard to FPGA Altera Corporation 2–17 July 2005 Nios Development Board Reference Manual, Stratix II Edition...
  • Page 26 Stratix II device. Unless otherwise noted, the labels indicate Stratix II device pin numbers. Figure 2–9. PROTO1 Expansion Prototype Connector - J15, J16 & J17 2–18 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...
  • Page 27 Figure 2–10. 6PROTO2 Pin Information - J15, J16 & J17 Notes to Figure 2–10 Unregulated voltage from DC power supply Clk from board oscillator Clk from FPGA via buffer Clk output from protocard to FPGA Altera Corporation 2–19 July 2005 Nios Development Board Reference Manual, Stratix II Edition...

  • Page 28: Compactflash Connector (Con3)

    The CompactFlash connector shares several Stratix II I/O pins with expansion prototype connector PROTO1. See “Expansion Prototype Connectors (PROTO1 & PROTO2)” on page 2–15 details on PROTO1. 2–20 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...
  • Page 29 CompactFlash pin out details. Table 2–6. CompactFlash (CON3) Pin Table (Part 1 of 2) Pin on CompactFlash CompactFlash Connects to Function (U60) (CON3) -CD2 -CD1 AB16 Altera Corporation 2–21 July 2005 Nios Development Board Reference Manual, Stratix II Edition...
  • Page 30 This pin does not connect to the FPGA directly. RESET is driven by the EPM7128AE configuration controller device. For more information on the CompactFlash connector (CON3), refer to www.compactflash.org and www.molex.com. 2–22 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 31: Mictor Connector (J25)

    Most pins on J25 connect to I/O pins on the Stratix II device (U60). For systems that do not use the Mictor connector for debugging the Nios II processor, any on-chip signals can be routed to I/O pins and probed at J25 via a Mictor cable.
  • Page 32 Mictor Connector (J25) Figure 2–13. Mictor Connector Signaling Figure 2–14. Debug Mictor Connector - J25 2–24 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 33: Configuration Controller Device (U3)

    Stratix II device. The Stratix II device is configured using fast passive parallel mode. For detailed information about the Altera EPM7128AE device, refer to the MAX 7000 family literature at www.altera.com/literature/lit- m7k.html.

  • Page 34: Factory & User Configurations

    Factory & User Configurations For details on programming configuration data to flash memory, see the Nios II Flash Programmer User Guide, or refer to the Nios II IDE online help. Factory & User The configuration controller can manage two separate Stratix II device configurations stored in flash memory.

  • Page 35: Flash Memory Partitions

    The lower 8 MB of flash memory is the user application space. This is free space for user designs to store code and data for Nios II programs. The lower 2 MB of the user application space is factory-programmed with code and data for a web server reference design.

  • Page 36: User Configuration

    The Nios II processor in the factory configuration is designed to start executing code from offset 0x00000000 in the flash memory. The Nios II development kit includes the source files for the factory-programmed hardware and software reference designs.

  • Page 37: Configuration-Status Leds

    This LED turns on when the factory configuration is being transferred from flash memory and stays illuminated if the factory configuration was successfully loaded into the Stratix II device. Figure 2–15. LED1 – LED4 Altera Corporation 2–29 July 2005 Nios Development Board Reference Manual, Stratix II Edition...

  • Page 38: Configuration & Reset Buttons

    When SW8 is pressed, a logic-0 is driven onto the Stratix II I/O pin AA15 (DEV_CLRn). The result of pressing SW8 depends on how the Stratix II device is currently configured. The factory-programmed Nios II reference design treats SW8 as a CPU- reset pin (see Figure 2–16).

  • Page 39: Jtag Connectors (J24 & J5)

    Altera download cable as shown in Figure 2–19. In addition, the Nios II IDE can access the Nios II processor JTAG debug module via a download cable connected to the J24 JTAG connector. Figure 2–18. JTAG Connector (J24) to Stratix II Device Altera Corporation 2–31...

  • Page 40: Jtag Connectors (J24 & J5)

    (J25). The pins of J24 are connected directly to pins on J25, and care must be taken so that signal contention does not occur between the two connectors. 2–32 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 41: Jtag Connector To Epm7128Ae Device (J5)

    JTAG Connector to EPM7128AE Device (J5) J5 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the EPM7128AE device (U3). Altera Quartus II software can perform in- system programming (ISP) to reprogram the EPM7128AE device (U3) with a new hardware image via an Altera download cable.
  • Page 42 ■ Drive the SDRAM chip (U57) via pin AF12, driven by on-chip PLL6. ■ Drive the Mictor connector (J25) clock via pin D13, driven by on-chip PLL5. 2–34 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 43: Power-Supply Circuitry

    ■ Feedback to FPGA pin N2 (CLK11p). This clock feedback path is not used by Altera-provided reference designs, but is available to the user if necessary. The 50 MHz oscillator (Y2) is socketed and can be changed or removed by the user.
  • Page 44 Power-Supply Circuitry 2–36 Altera Corporation Nios Development Board Reference Manual, Stratix II Edition July 2005...

  • Page 45: Shared Bus Table

    SRAM and Ethernet MAC/PHY devices share address and control lines. These shared lines are referred to as the Shared Bus. Using SOPC Builder, designers can interface a Nios II processor system to any device connected to the off-chip Shared Bus.
  • Page 46 Name FSE_D0 Shared Data FSE_D1 FSE_D2 FSE_D3 FSE_D4 FSE_D5 FSE_D6 FSE_D7 FSE_D8 FSE_D9 FSE_D10 FSE_D11 FSE_D12 FSE_D13 FSE_D14 FSE_D15 FSE_D16 FSE_D17 FSE_D18 FSE_D19 FSE_D20 FSE_D21 FSE_D22 FSE_D23 FSE_D24 FSE_D25 FSE_D26 FSE_D27 FSE_D28 FSE_D29 FSE_D30 FSE_D31 A–2 Altera Corporation July 2005...
  • Page 47 LCLK Clock ENET_LDEV_N Local Device LDEV# ENET_RDYRTN_N Ready Return RDYRTN ENET_W_R_N Write/Read W/R# Note to Table A–9: This pin is NC for AM29LV128M but is provided for compatible devices that have the active pin A23. Altera Corporation A–3 July 2005...

  • Page 48: Description

    Description A–4 Altera Corporation July 2005...

  • Page 49: Restoring The Factory Configuration

    To reprogram the flash memory on the development board, perform the following steps: the Flash Open a Nios II SDK Shell by choosing Windows Start > Programs > Memory Altera > Nios II Development Kit <installed version> > Nios II SDK Shell.

  • Page 50: Reprogramming The Epm7128Ae Configuration Controller Device

    Reprogramming the EPM7128AE Configuration Controller Device Click Add File and select the following programming file: <Nios II kit path>/examples/ factory_recovery/niosII_stratixII_2s60_ES/config_controller.pof. In the Programmer, check the Program/Configure box, and click Start to reprogram the EPM7128AE device. Press the Factory Config button to perform a power-on reset and reconfigure the Stratix II device from flash memory.

  • Page 51: Connecting To The Board Via Ethernet

    Figure C–1. Web Server Reference Design Connecting the The Nios II development kit includes an Ethernet (RJ45) cable and a male/female RJ45 crossover adapter. Before you connect these Ethernet Cable components, you must decide how you want to use the network features of your board.

  • Page 52: Connecting The Lcd Screen

    C–2). Figure C–2. Point-to-Point Connection Connecting the Your Nios II development kit was delivered with a two-line x 16- character LCD text screen. The web-server software displays useful status LCD Screen and progress messages on this display. If you wish to use the network features of the board, connect the LCD screen to the Expansion Prototype Connector (J12).

  • Page 53: Lan Connection

    Development Kit, Getting Started User Guide. Choose Start > Programs > Altera > Nios II Development Kit > Nios II SDK Shell to open the Nios II SDK Shell. A shell window appears with a command prompt. Press the SW9 button labeled Factory Config on the board.

  • Page 54: Point-To-Point Connections

    Nios II SDK Shell. Press the SW8 button labeled CPU Reset to reboot the Nios II processor and start the web server using the new IP address. The LCD screen will display the static IP address assigned to the board, along with other status messages.

  • Page 55: Browsing To Your Board

    IP address of the board (four numbers separated by decimal-points) as a URL directly into the browser’s Address input field. You can determine your board’s IP address by reading the messages displayed on the LCD screen Altera Corporation C–5 July 2005...

  • Page 56: July

    Browsing to Your Board C–6 Altera Corporation July 2005...

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