Mmu And Mpu Settings Tab - Altera Nios II User Manual

Chapter 4: Instantiating the Nios II Processor

MMU and MPU Settings Tab

ECC
ECC is only available for the Nios II/f core and provides ECC support for Nios II
internal RAM blocks, such as instruction cache, MMU TLB, and register file. The
SECDED ECC algorithm is based on Hamming codes, which detect 1 or 2 bit errors
and corrects 1 bit errors. If the Nios II processor does not attempt to correct any errors
and only detects them, the ECC algorithm can detect 3 bit errors.
f
Refer to
core.
MMU and MPU Settings Tab
The MMU and MPU Settings tab presents settings for configuring the MMU and
MPU on the Nios II processor. You can select the features appropriate for your target
application.
Table 4–4. MMU and MPU Settings Tab Parameters
Process ID (PID) bits
Optimize number of TLB entries
based on device family
TLB entries
TLB Set-Associativity
Micro DTLB entries
Micro ITLB entries
Use Limit for region range
Number of data regions
Minimum data region size
Number of instruction regions
Minimum instruction region
size
MMU
When Include MMU on the Core Nios II tab is on, the MMU settings on the MMU
and MPU Settings tab provide the following options for the MMU in the Nios II/f
core. Typically, you should not need to change any of these settings from their default
values.
■ Process ID (PID) bits—Specifies the number of bits to use to represent the process
identifier.
■ Optimize number of TLB entries based on device family—When on, specifies
the optimal number of TLB entries to allocate based on the device family of the
target hardware and disables TLB entries.
February 2014 Altera Corporation
"ECC" on page 5–13 for more information about ECC support in the Nios II/f
Name
Refer to
Refer to
Description
MMU
"MMU" on page 4–11.
MPU
"MPU" on page 4–12.
Nios II Processor Reference Handbook
4–11