Altera Nios II User Manual page 145

Chapter 5: Nios II Core Implementation Details
Nios II/s Core
■ An M-stage load/store instruction is waiting for Avalon-MM data master transfer
to complete.
An M-stage shift/rotate instruction is still performing its operation when using
■
the multicycle shift circuitry (i.e., when the hardware multiplier is not available).
An M-stage shift/rotate/multiply instruction is still performing its operation
■
when using the hardware multiplier (which takes three cycles).
■ An M-stage multicycle custom instruction is asserting its stall signal. This only
occurs if the design includes multicycle custom instructions.
Branch Prediction
The Nios II/s core performs static branch prediction to minimize the cycle penalty
associated with taken branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions have other
penalties associated with their execution. Instructions that flush the pipeline cause up
to three instructions after them to be cancelled. This creates a three-cycle penalty and
an execution time of four cycles. Instructions that require an Avalon-MM transfer are
stalled until the transfer completes.
Table 5–16. Instruction Execution Performance for Nios II/s Core
Normal ALU instructions (e.g., add, cmplt)
Combinatorial custom instructions
Multicycle custom instructions
Branch (correctly predicted taken)
Branch (correctly predicted not taken)
Branch (mispredicted)
trap, break, eret, bret,
flushp, wrctl, unimplemented
jmp, jmpi, ret, call, callr
rdctl
load, store
flushi, initi
Multiply
Divide
Shift/rotate (with hardware multiply using embedded
multipliers)
Shift/rotate (with hardware multiply using LE-based multipliers)
Shift/rotate (without hardware multiply present)
All other instructions
Note to
(1) Depends on the hardware multiply or divide option. Refer to
February 2014 Altera Corporation
Instruction
Table 5–16:
Cycles
1
1
> 1
2
1
4 Pipeline flush
4 Pipeline flush
4 Pipeline flush
1
> 1
4
(1)
(1)
3
4
1 to 32
1
Table 5–13 on page 5–16 for details.
Nios II Processor Reference Handbook
5–19
Penalties