Altera Nios II User Manual page 79

Chapter 3: Programming Model
Exception Processing
Shadow Register Sets
Although shadow register sets can be implemented independently of the EIC
interface, typically the two features are used together. Combining shadow register
sets with an appropriate EIC, you can minimize or eliminate the context switch
overhead for critical interrupts.
For the best interrupt performance, assign a dedicated register set to each of the most
time-critical interrupts. Less-critical interrupts can share register sets, provided the
ISRs are protected from register corruption as noted in
The method for mapping interrupts to register sets is specific to the particular EIC
implementation.
Internal Interrupt Controller
When the internal interrupt controller is implemented, a peripheral device can
request a hardware interrupt by asserting one of the Nios II processor's 32
interrupt-request inputs, irq0 through irq31. A hardware interrupt is generated if
and only if all three of these conditions are true:
The PIE bit of the status control register is one.
■
■ An interrupt-request input, irqn, is asserted.
■ The corresponding bit n of the ienable control register is one.
Upon hardware interrupt, the processor clears the PIE bit to zero, disabling further
interrupts, and performs the other steps outlined in
page
The value of the ipending control register shows which interrupt requests (IRQ) are
pending. By peripheral design, an IRQ bit is guaranteed to remain asserted until the
processor explicitly responds to the peripheral.
February 2014 Altera Corporation
3–45.
"Requested Register Set".
"Exception Processing Flow" on
Nios II Processor Reference Handbook
3–39