Jtag Debug Module Tab - Altera Nios II User Manual

Chapter 4: Instantiating the Nios II Processor

JTAG Debug Module Tab

JTAG Debug Module Tab
The JTAG Debug Module tab presents settings for configuring the JTAG debug
module on the Nios II processor. You can select the debug features appropriate for
your target application.
Table 4–5. JTAG Debug Module Tab Parameters
Debug level
Include debugreq and debugack
Signals
Break vector memory
Break vector offset
Break vector
OCI Onchip Trace
Automatically generate internal
2x clock signal
Soft processor cores such as the Nios II processor offer unique debug capabilities
beyond the features of traditional fixed processors. The soft nature of the Nios II
processor allows you to debug a system in development using a full-featured debug
core, and later remove the debug features to conserve logic resources. For the release
version of a product, you might choose to reduce the JTAG debug module
functionality, or remove it altogether.
Table 4–6. Debug Configuration Features
Feature
Connects to the processor through the standard JTAG pins on the Altera FPGA. This connection
JTAG Target Connection provides the basic capabilities to start and stop the processor, and examine/edit registers and
memory.
Download Software Downloads executable code to the processor's memory via the JTAG connection.
Software Breakpoints Sets a breakpoint on instructions residing in RAM.
Hardware Breakpoints Sets a breakpoint on instructions residing in nonvolatile memory, such as flash memory.
Triggers based on address value, data value, or read or write cycle. You can use a trigger to halt
the processor on specific events or conditions, or to activate other events, such as starting
Data Triggers
execution trace, or sending a trigger signal to an external logic analyzer. Two data triggers can be
combined to form a trigger that activates on a range of data or addresses.
Instruction Trace Captures the sequence of instructions executing on the processor in real time.
Captures the addresses and data associated with read and write operations executed by the
Data Trace
processor in real time.
On-Chip Trace Stores trace data in on-chip memory.
Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside the Nios II
Off-Chip Trace
core. Off-chip trace requires a debug probe from MIPS Technologies or Lauterbach GmbH.
February 2014 Altera Corporation
Name
Select a Debugging Level
Refer to
Refer to
Refer to
Advanced Debug Settings
Refer to
Description
"Debug Level Settings" on page
"Debug Signals" on page 4–15.
Break Vector
"Break Vector" on page 4–15.
"Advanced Debug Settings" on page
Description
Nios II Processor Reference Handbook
4–13
4–14.
4–15.