Altera Nios II User Manual page 81

Chapter 3: Programming Model
Exception Processing
■ Misaligned destination address
■ Division error
Fast TLB miss
■
■ Double TLB miss
■ TLB permission violation
■ MPU region violation
1
All noninterrupt exception handlers must run in the normal register set.
Trap Instruction
When a program issues the trap instruction, the processor generates a software trap
exception. A program typically issues a software trap when the program requires
servicing by the operating system. The general exception handler for the operating
system determines the reason for the trap and responds appropriately.
Break Instruction
The break instruction is treated as a break exception. For more information, refer to
"Break Exceptions" on page
Unimplemented Instruction
When the processor issues a valid instruction that is not implemented in hardware, an
unimplemented instruction exception is generated. The general exception handler
determines which instruction generated the exception. If the instruction is not
implemented in hardware, control is passed to an exception routine that might choose
to emulate the instruction in software. For more information, refer to
Unimplemented Instructions" on page
Illegal Instruction
Illegal instructions are instructions with an undefined opcode or opcode-extension
field. The Nios II processor can check for illegal instructions and generate an
exception when an illegal instruction is encountered. When your system contains an
MMU or MPU, illegal instruction checking is always on. When no MMU or MPU is
present, you have the option to have the processor check for illegal instructions.
f
For information about controlling this option, refer to the
Processor
When the processor issues an instruction with an undefined opcode or
opcode-extension field, and illegal instruction exception checking is turned on, an
illegal instruction exception is generated.
f
Refer to the OP Encodings and OPX Encodings for R-Type Instructions tables in the
Instruction Set Reference
unused opcodes and opcode extensions.
February 2014 Altera Corporation
3–36.
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook to see the
3–62.
Instantiating the Nios II
Nios II Processor Reference Handbook
3–41
"Potential