Altera Nios II User Manual page 274

8–94
sth / sthio
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31 30 29 28 27 26 25
A
31 30 29 28 27 26 25
A
Nios II Processor Reference Handbook
Mem16[rA + σ (IMM16)] ← rB
sth rB, byte_offset(rA)
sthio rB, byte_offset(rA)
sth r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Stores the low halfword of rB to the memory location specified by the
effective byte address. The effective byte address must be halfword aligned. If the byte address
is not a multiple of 2, the operation is undefined.
In processors with a data cache, this instruction may not generate an Avalon-MM data transfer
immediately. Use the sthio instruction for peripheral I/O. In processors with a data cache,
sthio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache, sthio acts like sth.
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
24 23 22 21 20 19 18 17
B
Instruction format for sth
24 23 22 21 20 19 18 17
B
Instruction format for sthio
store halfword to memory or I/O peripheral
15..0
16 15 14 13 12 11 10 9
IMM16
16 15 14 13 12 11 10 9
IMM16
Chapter 8: Instruction Set Reference
Instruction Set Reference
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
0x2d
February 2014 Altera Corporation
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