Altera Nios II User Manual page 143

Chapter 5: Nios II Core Implementation Details
Nios II/s Core
Memory Access
The Nios II/s core provides instruction cache, but no data cache. The instruction
cache size is user-definable, between 512 bytes and 64 KB. The Nios II/s core can
address up to 2 GB of external memory. The Nios II architecture reserves the
most-significant bit of data addresses for the bit-31 cache bypass method. In the
Nios II/s core, bit 31 is always zero.
f
For information regarding data cache bypass methods, refer to the
Architecture
Instruction and Data Master Ports
The instruction port on the Nios II/s core is optional. The instruction master port can
be excluded, as long as the core includes at least one tightly-coupled instruction
memory. The instruction master port is a pipelined Avalon-MM master port.
Support for pipelined Avalon-MM transfers minimizes the impact of synchronous
memory with pipeline latency. The pipelined instruction master port can issue
successive read requests before prior requests complete.
The data master port on the Nios II/s core is always present.
Instruction Cache
The instruction cache for the Nios II/s core is nearly identical to the instruction cache
in the Nios II/f core. The instruction cache memory has the following characteristics:
■ Direct-mapped cache implementation
The instruction master port reads an entire cache line at a time from memory, and
■
issues one read per clock cycle.
■ Critical word first
Table 5–14. Instruction Byte Address Fields
31 30 29 28 27 26 25
tag
The size of the tag field depends on the size of the cache memory and the physical
address size. The size of the line field depends only on the size of the cache memory.
The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte
address size is 31 bits.
The instruction cache is optional. However, excluding instruction cache from the
Nios II/s core requires that the core include at least one tightly-coupled instruction
memory.
Tightly-Coupled Memory
The Nios II/s core provides optional tightly-coupled memory interfaces for
instructions. A Nios II/s core can use up to four tightly-coupled instruction
memories. When a tightly-coupled memory interface is enabled, the Nios II core
includes an additional memory interface master port. Each tightly-coupled memory
interface must connect directly to exactly one memory slave port.
February 2014 Altera Corporation
chapter of the Nios II Processor Reference Handbook.
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
line
Processor
8 7 6 5 4 3 2 1
offset
Nios II Processor Reference Handbook
5–17
0