Document Revision History - Altera Nios II User Manual

2–22
■ Single sample of the data bus upon trigger event
Trace Frames
A frame is a unit of memory allocated for collecting trace data. However, a frame is
not an absolute measure of the trace depth.
To keep pace with the processor executing in real time, execution trace is optimized to
store only selected addresses, such as branches, calls, traps, and interrupts. From
these addresses, host-side debug software can later reconstruct an exact
instruction-by-instruction execution trace. Furthermore, execution trace data is stored
in a compressed format, such that one frame represents more than one instruction. As
a result of these optimizations, the actual start and stop points for trace collection
during execution might vary slightly from the user-specified start and stop points.
Data trace stores 100% of requested loads and stores to the trace buffer in real time.
When storing to the trace buffer, data trace frames have lower priority than execution
trace frames. Therefore, while data frames are always stored in chronological order,
execution and data trace are not guaranteed to be exactly synchronized with each
other.

Document Revision History

Table 2–7. Document Revision History (Part 1 of 2)
Date Version
February 2014 13.1.0
May 2011 11.0.0
December 2010 10.1.0
July 2010 10.0.0
November 2009 9.1.0
March 2009 9.0.0
November 2008 8.1.0
May 2008 8.0.0
October 2007 7.2.0
May 2007 7.1.0
March 2007 7.0.0
November 2006 6.1.0
Nios II Processor Reference Handbook
Added information on ECC support.
■
Added information on enhanced floating-point custom instructions.
■
Removed HardCopy information.
■
Removed references to SOPC Builder.
■
Added references to new Qsys system integration tool.
■
Moved interrupt vector custom instruction information to the Instantiating the Nios II
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Processor chapter.
Added reference to tightly-coupled memory tutorial.
Maintenance release.
Added external interrupt controller interface information.
■
Added shadow register set information.
■
Maintenance release.
Expanded floating-point instructions information.
■
Updated description of optional cpu_resetrequest and cpu_resettaken signals.
■
Added description of optional debugreq and debugack signals.
■
Added MMU and MPU sections.
Maintenance release.
Added table of contents to Introduction section.
■
Added Referenced Documents section.
■
Maintenance release.
Described interrupt vector custom instruction.
Chapter 2: Processor Architecture
Document Revision History
Changes
February 2014 Altera Corporation