Interrupt Exceptions - Altera Nios II User Manual

Chapter 3: Programming Model
Exception Processing
Returning From a Break
After processing a break, the break handler releases control of the processor by
executing a bret instruction. The bret instruction restores status by copying the
contents of bstatus and returns program execution to the address in the ba register
(r30) in the normal register set. Aside from bt and ba, all registers are guaranteed to
be returned to their pre-break state after returning from the break handler.

Interrupt Exceptions

A peripheral device can request an interrupt by asserting an interrupt request (IRQ)
signal. IRQs interface to the Nios II processor through an interrupt controller. You can
configure the Nios II processor with either of the following interrupt controller
options:
The external interrupt controller interface
■
■ The internal interrupt controller
External Interrupt Controller Interface
The Nios II EIC interface enables you to connect the Nios II processor to an external
interrupt controller component. The EIC can monitor and prioritize IRQ signals, and
determine which interrupt to present to the Nios II processor. An EIC can be
software-configurable.
The Nios II processor does not depend on any particular implementation of an EIC.
The degree of EIC configurability, and EIC configuration methods, are
implementation-specific. This section discusses the EIC interface, and general features
of EICs. For usage details, refer to the documentation for the specific EIC in your
system.
f
For a typical EIC implementation, refer to the Vectored Interrupt Controller chapter in
the Embedded Peripherals IP User
When an IRQ is asserted, the EIC presents the following information to the Nios II
processor:
■ The requested handler address (RHA)—Refer to
The requested interrupt level (RIL)—Refer to
■
The requested register set (RRS)—Refer to
■
■ Requested nonmaskable interrupt (RNMI) mode—Refer to
The Nios II processor EIC interface connects to a single EIC, but an EIC can support a
daisy-chained configuration. In a daisy-chained configuration, multiple EICs can
monitor and prioritize interrupts. The EIC directly connected to the processor
presents the processor with the highest-priority interrupt from all EICs in the daisy
chain.
An EIC component can support an arbitrary level of daisy-chaining, potentially
allowing the Nios II processor to handle an arbitrary number of prioritized interrupts.
February 2014 Altera Corporation
Guide.
"Requested Handler Address"
"Requested Interrupt Level"
"Requested Register Set"
3–37
"Requested NMI Mode"
Nios II Processor Reference Handbook