Altera Nios II User Manual page 137

Chapter 5: Nios II Core Implementation Details
Nios II/f Core
■ An A-stage multicycle custom instruction is asserting its stall signal. This only
occurs if the design includes multicycle custom instructions.
The D-stage stall occurs if an instruction is trying to use the result of a late result
instruction too early and no M-stage pipeline flush is active. The late result
instructions are loads, shifts, rotates, rdctl, multiplies (if hardware multiply is
supported), divides (if hardware divide is supported), and multicycle custom
instructions (if present).
Branch Prediction
The Nios II/f core performs dynamic branch prediction to minimize the cycle penalty
associated with taken branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions have other
penalties associated with their execution. Late result instructions have two cycles
placed between them and an instruction that uses their result. Instructions that flush
the pipeline cause up to three instructions after them to be cancelled. This creates a
three-cycle penalty and an execution time of four cycles. Instructions that require
Avalon-MM transfers are stalled until any required Avalon-MM transfers (up to one
write and one read) are completed.
Table 5–10. Instruction Execution Performance for Nios II/f Core 4byte/line data cache (Part 1 of 2)
Normal ALU instructions (e.g., add, cmplt)
Combinatorial custom instructions
Multicycle custom instructions
Branch (correctly predicted, taken)
Branch (correctly predicted, not taken)
Branch (mispredicted)
trap, break, eret, bret, flushp, wrctl, wrprs; illegal and unimplemented instructions
call, jmpi, rdprs
jmp, ret, callr
rdctl
load (without Avalon-MM transfer)
load (with Avalon-MM transfer)
store (without Avalon-MM transfer)
store (with Avalon-MM transfer)
flushd, flushda (without Avalon-MM transfer)
flushd, flushda (with Avalon-MM transfer)
initd, initda
flushi, initi
Multiply
Divide
Shift/rotate (with hardware multiply using embedded multipliers)
February 2014 Altera Corporation
Instruction
5–11
Cycles Penalties
1
1
> 1 Late result
2
1
4 Pipeline flush
4 or 5 (2) Pipeline flush
2
3
1 Late result
1 Late result
> 1 Late result
1
> 1
2
> 2
2
4
(1) Late result
(1) Late result
1 Late result
Nios II Processor Reference Handbook