Altera Nios II User Manual page 89

Chapter 3: Programming Model
Exception Processing
Table 3–1.
Notes to Table 3–37:
(1) If the Nios II processor does not have an EIC interface, external interrupts do not occur.
(2) If the Nios II processor does not have an MMU, this field is not implemented. Its value is always 0, and the processor behaves accordingly.
(3) If the Nios II processor does not have shadow register sets, this field is not implemented. Its value is always 0, and the processor behaves
accordingly.
(4) If the Nios II processor does not have an MMU, TLB-related exceptions do not occur.
(5) If the Nios II processor does not have an MMU, this register is not implemented.
(6) The VPN of the address triggering the exception
(7) The pre-exception value
(8) Invokes the general exception handler
(9) Invokes the fast TLB miss exception handler
(10) If the Nios II processor does not have shadow register sets, this register is not implemented.
(11) Saves the processor's pre-exception status
(12) sstatus.SRS is set to 1 if RRS is not equal to status.CRS.
(13) The address following the instruction being executed when the exception occurs
(14) Set to 1 on a data access exception, set to 0 otherwise
(15) Set to 1 on a double TLB miss, set to 0 otherwise
(16) Set to 1 on a TLB permission violation, set to 0 otherwise
(17) Set to 1 on a bad virtual address exception, set to 0 otherwise
(18) Disables exceptions and nonmaskable interrupts, unless automatic nested interrupts are explicitly enabled by config.ANI
(19) Disables exceptions and nonmaskable interrupts
(20) If the MMU is implemented, indicates that the processor is handling an exception.
(21) If the Nios II processor does not have an EIC interface, this field is not implemented.
(22) Puts the processor in supervisor mode.
Determining the Cause of Interrupt and Instruction-Related Exceptions
The general exception handler must determine the cause of each exception and then
transfer control to an appropriate exception routine.
With Extra Exception Information
When you have included the extra exception information in your Nios II system, the
CAUSE field of the exception register (refer to
contains a code for the highest-priority exception occurring at the time and the BADDR
field of the badaddr register (refer to
the byte instruction address or data address for certain exceptions. Refer to
on page 3–33
1
External interrupts do not set exception.CAUSE.
To determine the cause of an exception, simply read the cause of the exception from
exception.CAUSE and then transfer control to the appropriate exception routine.
1
Extra exception information is always enabled in Nios II systems containing an MMU
or MPU.
February 2014 Altera Corporation
"The badaddr Register" on page
for more information.
"The exception Register" on page
Nios II Processor Reference Handbook
3–49
3–15)
3–19) contains
Table 3–35