Processor Implementation - Altera Nios II User Manual

2–2
Figure 2–1. Nios II Processor Core Block Diagram
reset
clock
cpu_resetrequest
cpu_resettaken
JTAG
interface
to software
debugger
irq[31..0]
eic_port_data[44..0]
eic_port_valid
Custom
I/O
Signals

Processor Implementation

The functional units of the Nios II architecture form the foundation for the Nios II
instruction set. However, this does not indicate that any unit is implemented in
hardware. The Nios II architecture describes an instruction set, not a particular
hardware implementation. A functional unit can be implemented in hardware,
emulated in software, or omitted entirely.
A Nios II implementation is a set of design choices embodied by a particular Nios II
processor core. All implementations support the instruction set defined in the
Instruction Set Reference
implementation achieves specific objectives, such as smaller core size or higher
performance. This flexibility allows the Nios II architecture to adapt to different target
applications.
Nios II Processor Reference Handbook
Nios II Processor Core
Program
Controller
&
Address
Generation
JTAG
Exception
Debug Module
Controller
Internal
Interrupt
Controller
External
Interrupt
Controller
Interface
Custom
Instruction
Arithmetic
Logic
Logic Unit
Key
Required
Module
chapter of the Nios II Processor Reference Handbook. Each
General
Purpose
Registers
Instruction
Control
Cache
Registers
Shadow
Register
Sets
Instruction
Memory
Regions
Management
Unit
Memory
Protection
Unit
Translation
Lookaside
Data
Buffer
Regions
Data
Cache
Optional
Module
Chapter 2: Processor Architecture
Processor Implementation
Tightly Coupled
Instruction Memory
Tightly Coupled
Instruction Memory
Instruction Bus
Data Bus
Tightly Coupled
Data Memory
Tightly Coupled
Data Memory
February 2014 Altera Corporation