Altera Nios II User Manual page 49

Chapter 3: Programming Model
Memory Protection Unit
Region Size or Upper Address Limit
A Qsys generation-time option controls whether the amount of memory in the region
is defined by size or upper address limit. The size is an integer power of two bytes.
The limit is the highest address of the region plus one. The minimum supported
region size is 64 bytes but can be configured for larger minimum sizes to save logic
resources. The maximum supported region size equals the Nios II address space (a
function of the address ranges of slaves connected to the Nios II masters). Any access
outside of the Nios II address space is considered not to match any region and triggers
an MPU region violation exception.
When regions are defined by size, the size is encoded as a binary mask to facilitate the
following MPU region address range matching:
(address & region_mask) == region_base_address
When regions are defined by limit, the limit is encoded as an unsigned integer to
facilitate the following MPU region address range matching:
(address >= region_base) && (address < region_limit)
The region limit uses a less-than instead of a less-than-or-equal-to comparison
because less-than provides a more efficient implementation. The limit is one bit larger
than the address so that full address range may be included in a range. Defining the
region by limit results in slower and larger address range match logic than defining
by size but allows finer granularity in region sizes.
Access Permissions
The access permissions consist of execute permissions for instruction regions and
read/write permissions for data regions. Any instruction that performs a memory
access that violates the access permissions triggers an exception. Additionally, any
instruction that performs a memory access that does not match any region triggers an
exception.
Default Cacheability
The default cacheability specifies whether normal load and store instructions access
the data cache or bypass the data cache. The default cacheability is only present for
data regions. You can override the default cacheability by using the ldio or stio
instructions. The bit 31 cache bypass feature is available when the MPU is present.
Refer to the Cache Memory section for more information on cache bypass.
Overlapping Regions
The memory addresses of regions can overlap. Overlapping regions have several uses
including placing markers or small holes inside of a larger region. For example, the
stack and heap may be located in the same region, growing from opposite ends of the
address range. To detect stack/heap overflows, you can define a small region between
the stack and heap with no access permissions and assign it a higher priority than the
larger region. Any access attempts to the hole region trigger an exception informing
system software about the stack/heap overflow.
If regions overlap so that a particular access matches more than one region, the region
with the highest priority (lowest index) determines the access permissions and default
cacheability.
February 2014 Altera Corporation Nios II Processor Reference Handbook
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