Altera Nios II User Manual page 52

3–12
The status Register
The value in the status register determines the state of the Nios II processor. All
status bits are set to predefined values at processor reset. Some bits are exclusively
used by and available only to certain features of the processor, such as the MMU,
MPU or external interrupt controller (EIC) interface.
Table 3–7. status Control Register Fields
31 30 29 28 27 26 25
Reserved
Table 3–8. status Control Register Field Descriptions (Part 1 of 2)
Bit
RSIE is the register set interrupt-enable bit. When set to 1, this bit allows
the processor to service external interrupts requesting the register set that
RSIE
is currently in use. When set to 0, this bit disallows servicing of such
interrupts.
NMI is the nonmaskable interrupt mode bit. The processor sets NMI to 1
NMI
when it takes a nonmaskable interrupt.
PRS is the previous register set field. The processor copies the CRS field to
the PRS field upon one of the following events:
In a processor with no MMU, on any exception
■
In a processor with an MMU, on one of the following:
■
Break exception
■
Nonbreak exception when status.EH is zero
■
The processor copies CRS to PRS immediately after copying the status
register to estatus, bstatus or sstatus.
PRS
The number of significant bits in the CRS and PRS fields depends on the
number of shadow register sets implemented in the Nios II core. The value
of CRS and PRS can range from 0 to n-1, where n is the number of
implemented register sets. The processor core implements the number of
significant bits needed to represent n-1. Unused high-order bits are always
read as 0, and must be written as 0.
1
Ensure that system software writes only valid register set numbers to
the PRS field. Processor behavior is undefined with an unimplemented
register set number.
CRS is the current register set field. CRS indicates which register set is
currently in use. Register set 0 is the normal register set, while register sets
1 and higher are shadow register sets. The processor sets CRS to zero on
any noninterrupt exception.
CRS
The number of significant bits in the CRS and PRS fields depends on the
number of shadow register sets implemented in the Nios II core. Unused
high-order bits are always read as 0, and must be written as 0.
Nios II Processor Reference Handbook
24 23 22 21 20 19 18 17
PRS
Description
16 15 14 13 12 11 10 9
CRS
Chapter 3: Programming Model
Registers
8 7 6 5 4 3 2
IL
Access Reset Available
EIC
interface
and shadow
Read/Write 1
register
sets
only
EIC
Read 0 interface
only
Shadow
register
Read/Write 0
sets
only
Shadow
register
Read (1) 0
sets
only
February 2014 Altera Corporation
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