Altera Nios II User Manual page 62

3–22
The mpuacc Register
The mpuacc register works in conjunction with the mpubase register to set and retrieve
MPU region information and is only available in systems with an MPU. The mpuacc
register consists of attributes that will be set or have been retrieved which define the
MPU region. The mpuacc register only holds a portion of the attributes that define an
MPU region. The remaining portion of the MPU region definition is held by the BASE
field of the mpubase register.
A Qsys generation-time option controls whether the mpuacc register contains a MASK or
LIMIT field.
Table 3–25. mpuacc Control Register Fields for MASK Variation
31 30 29 28 27 26 25
0
Note:
(1) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
Table 3–26. mpuacc Control Register Fields for LIMIT Variation
31 30 29 28 27 26 25
Note:
(1) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
Table 3–27. mpuacc Control Register Field Descriptions
Field
(1) MASK specifies the size of the region.
MASK
(1) LIMIT specifies the upper address limit of the region.
LIMIT
C is the data cacheable flag. C only applies to MPU data regions and
determines the default cacheability of a data region. When C = 0, the
C
data region is uncacheable. When C = 1, the data region is
cacheable.
PERM specifies the access permissions for the region.
PERM
RD is the read region flag. When RD = 1, wrctl instructions to the
RD
mpuacc register perform a read operation.
WR is the write region flag. When WR = 1, wrctl instructions to the
WR
mpuacc register perform a write operation.
Note:
(1) The MASK and LIMIT fields are mutually exclusive. Refer to mpucc Control Register Field for MASK Variation Table and mpuacc Control Register
Field for LIMIT Variation Table.
The following sections provide more information about the mpuacc fields.
Nios II Processor Reference Handbook
24 23 22 21 20 19 18 17
(1)
MASK
24 23 22 21 20 19 18 17
(1)
LIMIT
Description
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
Read/Write
Read/Write
Read/Write
Read/Write
Chapter 3: Programming Model
8 7 6 5 4 3 2
C PERM
8 7 6 5 4 3 2
C PERM
Access Reset Available
Only with
0
MPU
Only with
0
MPU
Only with
0
MPU
Only with
0
MPU
Only with
Write 0
MPU
Only with
Write 0
MPU
February 2014 Altera Corporation
Registers
1 0
1 0